MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 35

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.6 Peripheral Memory Mapped Registers
On-chip peripheral registers are part of the data memory map on the 56800E series. These locations may
be accessed with the same addressing modes used for ordinary Data memory, except all peripheral
registers should be read/written using word accesses only.
Table 4-8
Peripherals are listed in order of the base address.
The following tables list all of the peripheral registers required to control or access the peripherals.
Freescale Semiconductor
TMR0_COMP1
TMR0_COMP2
TMR0_CAPT
TMR0_LOAD
TMR0_HOLD
TMR0_CNTR
TMR0_CTRL
TMR0_SCTRL
TMR0_CMPLD1
Timer
PWM
ITCN
ADC
SCI
SPI
I
COP
CLK, PLL, OSC, TEST
GPIO Port A
GPIO Port B
GPIO Port C
GPIO Port D
SIM
Power Supervisor
FM
2
summarizes base addresses for the set of peripherals on the 56F8013/56F8011 device.
C
Register Acronym
Table 4-8 Data Memory Peripheral Base Address Map Summary
Peripheral
Table 4-9 Quad Timer Registers Address Map
Address Offset
56F8013/56F8011 Data Sheet, Rev. 12
(TMR_BASE = $00 F000)
$0
$1
$2
$3
$4
$5
$6
$7
$8
TMRn
PWM
ITCN
ADC
SCI
SPI
I2C
COP
OCCS
GPIOA
GPIOB
GPIOC
GPIOD
SIM
PS
FM
Prefix
Compare Register 1
Compare Register 2
Capture Register
Load Register
Hold Register
Counter Register
Control Register
Status and Control Register
Comparator Load Register 1
Base Address
X:$00 F0C0
X:$00 F0D0
X:$00 F0B0
X:$00 F0E0
X:$00 F0F0
Register Description
X:$00 F000
X:$00 F040
X:$00 F060
X:$00 F080
X:$00 F100
X:$00 F110
X:$00 F120
X:$00 F130
X:$00 F140
X:$00 F160
X:$00 F400
Peripheral Memory Mapped Registers
Table Number
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-9
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