MC56F8013VFAE Freescale Semiconductor, MC56F8013VFAE Datasheet - Page 73

• Manufacturer Part Number: MC56F8013VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8013VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Rom Size: 16 KB
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEMDEMO56F8013-EE - BOARD DEMO FOR 56F8013
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.3.8
All of the peripheral pins on the 56F8013/56F8011 share their Input/Output (I/O) with GPIO ports. To
select peripheral or GPIO control, program corresponding bit in the GPIOx_PEREN register in GPIO
module. See the 56F801x Peripheral Reference Manual for detail. In some cases, there are two possible
peripherals as well as the GPIO functionality available for control of the I/O. In these cases, the SIM_GPS
register is used to determine which peripheral has control when the corresponding I/O pin is configured in
peripheral mode.
As shown in
pin controls the I/O. SIM_GPS simply decides which peripheral will be routed to the I/O when
PEREN = 1.
Freescale Semiconductor
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Base + $B
RESET
01001 = Reserved for factory test—OCCS MSTR OSC clock
01011 = Reserved for factory test—ADC clock
01100 = Reserved for factory test—JTAG TCLK
01101 = Reserved for factory test—Continuous peripheral clock
01110 = Reserved for factory test—Continuous inverted peripheral clock
01111 = Reserved for factory test—Continuous high-speed peripheral clock
Read
Write
SIM GPIO Peripheral Select Register (SIM_GPS)
Figure
TCR
15
Figure 6-9 Overall Control of Pads Using SIM_GPS Control
0
Figure 6-10 GPIO Peripheral Select Register (SIM_GPS)
6-9, the GPIO Peripheral Enable Register (PEREN) has the final control over which
PCR
14
Quad Timer Controlled
0
13
0
0
SCI Controlled
12
0
0
SIM_GPS Register
CFG_
56F8013/56F8011 Data Sheet, Rev. 12
11
B7
0
GPIO Controlled
CFG_
10
B6
0
CFG_
B5
9
0
0
1
GPIOB_PEREN Register
CFG_
B4
8
0
CFG_
B3
7
0
0
1
CFG_
B2
6
0
I/O Pad Control
CFG_
B1
5
0
CFG_
B0
4
0
3
0
CFG_A5
2
0
Register Descriptions
1
0
CFG_A4
0
0
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