C8051F064-GQ Silicon Laboratories Inc, C8051F064-GQ Datasheet - Page 134

• Manufacturer Part Number: C8051F064-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F064-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Data Rom Size: 64 KB
• A/d Bit Size: 16 bit
• A/d Channels Available: 1
• Height: 1.05 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1219 - KIT EVAL FOR C8051F064
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1218

C8051F060/1/2/3/4/5/6/7
13.2.6.3.SFR Page Stack Example
The following is an example that shows the operation of the SFR Page Stack during interrupts.
In this example, the SFR Page Control is left in the default enabled state (i.e., SFRPGEN = 1), and the
CIP-51 is executing in-line code that is writing values to Port 5 (SFR “P5”, located at address 0xD8 on SFR
Page 0x0F). The device is also using the Programmable Counter Array (PCA) and the 10-bit ADC (ADC2)
window comparator to monitor a voltage. The PCA is timing a critical control function in its interrupt service
routine (ISR), so its interrupt is enabled and is set to high priority. The ADC2 is monitoring a voltage that is
less important, but to minimize the software overhead its window comparator is being used with an associ-
ated ISR that is set to low priority. At this point, the SFR page is set to access the Port 5 SFR (SFRPAGE =
0x0F). See Figure 13.4 below.
Figure 13.4. SFR Page Stack While Using SFR Page 0x0F To Access Port 5
SFR Page
Stack SFR's
0x0F
SFRPAGE
(Port 5)
SFRNEXT
SFRLAST
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Rev. 1.2