C8051F064-GQ Silicon Laboratories Inc, C8051F064-GQ Datasheet - Page 206

• Manufacturer Part Number: C8051F064-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F064-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Data Rom Size: 64 KB
• A/d Bit Size: 16 bit
• A/d Channels Available: 1
• Height: 1.05 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1219 - KIT EVAL FOR C8051F064
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1218

C8051F060/1/2/3/4/5/6/7
eral’s enable bits are not set to a logic 1, then its ports are not accessible at the Port pins of the device.
Also note that the Crossbar assigns pins to all associated functions when the SMBus, UART0 or UART1
are selected (i.e. SMBus, SPI, UART). It would be impossible, for example, to assign TX0 to a Port pin
without assigning RX0 as well. The SPI can operate in 3 or 4-wire mode (with or without NSS). Each com-
bination of enabled peripherals results in a unique device pinout.
All Port pins on Ports 0 through 3 that are not allocated by the Crossbar can be accessed as General-Pur-
pose I/O (GPIO) pins by reading and writing the associated Port Data registers (See Figure 18.9,
Figure 18.11, Figure 18.14, and Figure 18.17), a set of SFRs which are both byte- and bit-addressable.
The output states of Port pins that are allocated by the Crossbar are controlled by the digital peripheral that
is mapped to those pins. Writes to the Port Data registers (or associated Port bits) will have no effect on
the states of these pins.
A Read of a Port Data register (or Port bit) will always return the logic state present at the pin itself, regard-
less of whether the Crossbar has allocated the pin for peripheral use or not. An exception to this occurs
during the execution of a read-modify-write instruction (ANL, ORL, XRL, CPL, INC, DEC, DJNZ, JBC,
CLR, SETB, and the bitwise MOV write operation). During the read cycle of the read-modify-write instruc-
tion, it is the contents of the Port Data register, not the state of the Port pins themselves, which is read.
Because the Crossbar registers affect the pinout of the peripherals of the device, they are typically config-
ured in the initialization code of the system before the peripherals themselves are configured. Once config-
ured, the Crossbar registers are typically left alone.
Once the Crossbar registers have been properly configured, the Crossbar is enabled by setting XBARE
(XBR2.4) to a logic 1. Until XBARE is set to a logic 1, the output drivers on Ports 0 through 3 are
explicitly disabled in order to prevent possible contention on the Port pins while the Crossbar reg-
isters and other registers which can affect the device pinout are being written.
The output drivers on Crossbar-assigned input signals (like RX0, for example) are explicitly disabled; thus
the values of the Port Data registers and the PnMDOUT registers have no effect on the states of these
pins.
18.1.2. Configuring the Output Modes of the Port Pins
The output drivers on Ports 0 through 3 remain disabled until the Crossbar is enabled by setting XBARE
(XBR2.4) to a logic 1.
The output mode of each port pin can be configured to be either Open-Drain or Push-Pull. In the Push-Pull
configuration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be
driven to GND, and writing a logic 1 will cause the Port pin to be driven to VDD. In the Open-Drain configu-
ration, writing a logic 0 to the associated bit in the Port Data register will cause the Port pin to be driven to
GND, and a logic 1 will cause the Port pin to assume a high-impedance state. The Open-Drain configura-
tion is useful to prevent contention between devices in systems where the Port pin participates in a shared
interconnection in which multiple outputs are connected to the same physical wire (like the SDA signal on
an SMBus connection).
The output modes of the Port pins on Ports 0 through 3 are determined by the bits in the associated
PnMDOUT registers (See Figure 18.10, Figure 18.13, Figure 18.16, and Figure 18.18). For example, a
logic 1 in P3MDOUT.7 will configure the output mode of P3.7 to Push-Pull; a logic 0 in P3MDOUT.7 will
configure the output mode of P3.7 to Open-Drain. All Port pins default to Open-Drain output.
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Rev. 1.2