C8051F064-GQ Silicon Laboratories Inc, C8051F064-GQ Datasheet - Page 67

• Manufacturer Part Number: C8051F064-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F064-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Data Rom Size: 64 KB
• A/d Bit Size: 16 bit
• A/d Channels Available: 1
• Height: 1.05 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1219 - KIT EVAL FOR C8051F064
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1218

AINnG
The offset register value affects the offset at the analog input as follows:
The gain register value affects the slope of the ADC transfer function as follows:
AINn
Offset Register (14 Bits)
Gain Register (13 Bits)
0x3FFF
0x1FFF
0x2000
0x0000
0x1000
0x0000
Figure 5.21. Offset and Gain Calibration Block Diagram
Offset Change
Figure 5.20. Offset and Gain Register Mapping
Slope Change
+
Offset
-

0x2000 Offset Register
----------------------------------------------------------- -

Gain Register 0x1000
-------------------------------------------------------- -
Approximate Offset Change (V)
Approximate Slope Change
–
Rev. 1.2
8192
ADCn
VREF
+3.125% * VREF
-3.125% * VREF
4096
+
C8051F060/1/2/3/4/5/6/7
+3.125%
-3.125%
–
0
0
Gain

3.125% VREF

3.125%
16

ADCn Data
67