C8051F064-GQ Silicon Laboratories Inc, C8051F064-GQ Datasheet - Page 156

IC 8051 MCU 64K FLASH 100TQFP

C8051F064-GQ

Manufacturer Part Number
C8051F064-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Datasheets

Specifications of C8051F064-GQ

Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
59
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
59
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F060DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit, 1 Channel
On-chip Dac
12 bit, 2 Channel
No. Of I/o's
59
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Package
100TQFP
Device Core
8051
Family Name
C8051F06x
Maximum Speed
25 MHz
Data Rom Size
64 KB
A/d Bit Size
16 bit
A/d Channels Available
1
Height
1.05 mm
Length
14 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Width
14 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1219 - KIT EVAL FOR C8051F064
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1218

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Part Number:
C8051F064-GQR
0
C8051F060/1/2/3/4/5/6/7
156
Bit7:
Bit6:
Bit6:
Bit6:
Bit3:
Bit2:
Bit1:
Bit0:
EADC0
R/W
Bit7
EADC0: Enable ADC0 End of Conversion Interrupt.
This bit sets the masking of the ADC0 End of Conversion Interrupt.
0: Disable ADC0 Conversion Interrupt.
1: Enable interrupt requests generated by the ADC1 Conversion Interrupt.
CP2IE: Enable Comparator (CP2) Interrupt.
This bit sets the masking of the CP2 interrupt.
0: Disable CP2 interrupts.
1: Enable interrupt requests generated by the CP2IF flag.
CP1IE: Enable Comparator (CP1) Interrupt.
This bit sets the masking of the CP1 interrupt.
0: Disable CP1 interrupts.
1: Enable interrupt requests generated by the CP1IF flag.
CP0IE: Enable Comparator (CP0) Interrupt.
This bit sets the masking of the CP0 interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0IF flag.
EPCA0: Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
EWADC0: Enable Window Comparison ADC0 Interrupt.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison Interrupt.
1: Enable Interrupt requests generated by ADC0 Window Comparisons.
ESMB0: Enable System Management Bus (SMBus0) Interrupt.
This bit sets the masking of the SMBus interrupt.
0: Disable all SMBus interrupts.
1: Enable interrupt requests generated by the SI flag.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of SPI0 interrupt.
0: Disable all SPI0 interrupts.
1: Enable Interrupt requests generated by the SPI0 flag.
CP2IE
R/W
Bit6
CP1IE
Figure 13.21. EIE1: Extended Interrupt Enable 1
R/W
Bit5
CP0IE
R/W
Bit4
Rev. 1.2
EPCA0
R/W
Bit3
EWADC0
R/W
Bit2
ESMB0
R/W
Bit1
SFR Address:
SFR Page:
ESPI0
R/W
Bit0
0xE6
All Pages
Reset Value
00000000

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