C8051F064-GQ Silicon Laboratories Inc, C8051F064-GQ Datasheet - Page 319

• Manufacturer Part Number: C8051F064-GQ
• Description: IC 8051 MCU 64K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F064-GQ

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 59
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 59
• Ram Memory Size: 4352Byte
• Cpu Speed: 25MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F06x
• Maximum Speed: 25 MHz
• Data Rom Size: 64 KB
• A/d Bit Size: 16 bit
• A/d Channels Available: 1
• Height: 1.05 mm
• Length: 14 mm
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1219 - KIT EVAL FOR C8051F064
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1218

EXTEST provides access to both capture and update actions, while Sample only performs a capture.
102, 104, 106, 108
103, 105, 107, 109
110, 112, 114, 116,
118, 120, 122, 124
111, 113, 115, 117,
119, 121, 123, 125
79, 81, 83, 85, 87,
94, 96, 98, 100,
95, 97, 99, 101,
89, 91, 93
Bit
Table 26.1. Boundary Data Register Bit Definitions (C8051F060/2/4/6) (Continued)
Action
Capture P5.n input from pin (follows P0.n numbering scheme)
Update
Capture P6.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P6.n input from pin (follows P0.n numbering scheme)
Update
Capture P7.n output enable from MCU (follows P0.n numbering scheme)
Update
Capture P7.n input from pin (follows P0.n numbering scheme)
Update
Target
P5.n output to pin (follows P0.n numbering scheme)
P6.n output enable to pin (follows P0.n numbering scheme)
P6.n output to pin (follows P0.n numbering scheme)
P7.n output enable to pin (follows P0.n numbering scheme)
P7.n output to pin (follows P0.n numbering scheme)
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
319