HD64F7047F50V Renesas Electronics America, HD64F7047F50V Datasheet - Page 370
HD64F7047F50V
Manufacturer Part Number
HD64F7047F50V
Description
IC H8 MCU FLASH 256K 100TQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7047r
Specifications of HD64F7047F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
53
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
12K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Package
100PQFP
Family Name
SuperH
Maximum Speed
50 MHz
Operating Supply Voltage
5 V
Data Bus Width
32 Bit
Number Of Programmable I/os
53
Interface Type
CAN/SCI
On-chip Adc
16-chx10-bit
Number Of Timers
7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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11.6.5
If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly.
Avoid logical input of the WDTOVF signal to the RES input pin. To reset the entire system with
the WDTOVF signal, use the circuit shown in figure 11.9.
11.6.6
If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a
TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset.
11.6.7
When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits
until the end of the bus cycle at the time of manual reset generation before making the transition to
manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a
manual reset occurs while the bus is released, manual reset exception processing will be deferred
until the CPU acquires the bus. However, if the interval from generation of the manual reset until
the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles,
the internal manual reset source is ignored instead of being deferred, and manual reset exception
processing is not executed.
11.6.8
Do not pull-down the WDTOVF pin. If this pin need to be pulled-down, the pull-down resistance
value must be 1 MΩ or higher.
Rev. 2.00, 09/04, page 328 of 720
Reset signal to entire system
System Reset by WDTOVF Signal
Internal Reset in Watchdog Timer Mode
Manual Reset in Watchdog Timer Mode
Handling of WDTOVF pin
Figure 11.9 Example of System Reset Circuit Using WDTOVF Signal
Reset input
RES
WDTOVF
This LSI
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