MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet

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... Freescale Semiconductor, Inc. Advance Information MCF5407PB/D Rev. 3.3, 2/2003 MCF5407 Integrated ® ColdFire Microprocessor Product Brief This document is an overview of the MCF5407 ColdFire processor, focusing on feature enhancements over the MCF5307. It includes general descriptions of features and of the various modules incorporated in the MCF5407. It describes the V4 programming model implemented in the MCF5407 ...

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... Freescale Semiconductor, Inc. Features JTAG Debug Module ÷2 PSTCLK CLKIN Local Memory (to on-chip Instruction Bus peripherals) CLKIN PCLK PLL Xn RSTI RSTO SYSTEM INTEGRATION MODULE (SIM) PLL Control System Control PLL RSR SWIVR SYPCR SWSR DRAM Controller Chip-Select Module DRAM Control 8 8 DCR ...

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... Freescale Semiconductor, Inc. Although the MCF5407 offers obvious performance upgrade advantages, its rich memory and peripheral integration at inexpensive prices should not be overlooked. Features common to many embedded applications, such as DMAs, various DRAM controller interfaces, and on-chip memories, are integrated in a cost-effective manner using aggressive process technologies. ...

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... Freescale Semiconductor, Inc. MCF5407 Features — Two independent decoupled pipelines: four-stage instruction fetch pipeline (IFP) and five-stage operand execution pipeline (OEP) — Ten-instruction FIFO buffer provides decoupling between the pipelines — Limited superscalar design achieves performance levels close to dual-issue performance — Programmable two-level branch acceleration mechanism with an 8-entry branch cache plus a 128-entry prediction table for increased performance — ...

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... Freescale Semiconductor, Inc. — Operand packing and unpacking supported — Auto-alignment transfers supported for efficient block movement — Supports bursting and cycle steal — Provides two bus clock internal access — Automatic DMA transfers from on-chip UARTs using internal interrupts • ...

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... Freescale Semiconductor, Inc. ColdFire Module Description • 16-bit general-purpose I/O interface • IEEE 1149.1 test (JTAG) module • System debug support — Real-time trace for determining dynamic execution path while in emulator mode — Background debug mode (BDM) for debug features while halted — ...

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... Freescale Semiconductor, Inc. time stalled waiting for instructions. To maximize the performance of conditional branch instructions, the Version 4 IFP implements a sophisticated two-level acceleration mechanism. The first level is an 8-entry, direct-mapped branch cache with a 2-bit prediction state (strongly/weakly, taken/not-taken) for each entry. The branch cache implements instruction folding techniques that allow conditional branch instructions which are predicted correctly as taken to execute in zero cycles ...

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... Freescale Semiconductor, Inc. ColdFire Module Description 1.3.2 Harvard Architecture A Harvard memory architecture is implemented to support the increased bandwidth requirements of the V4 processor pipelines. In this design featuring separate instruction and data buses to the processor-local memories, available bandwidth to the processor reaches 1.3 Gbytes/S at 162 MHz and conflicts between instruction fetches and operand accesses are removed ...

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... Freescale Semiconductor, Inc. 1.3.5 UART Modules The MCF5407 contains two UARTs, which function independently. One UART has been enhanced to provide synchronous operation and a CODEC interface for soft modem support. Each UART can be clocked by the system bus clock, eliminating the need for an external crystal. Each UART module interfaces directly to the CPU, as shown in Figure 2 ...

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... Freescale Semiconductor, Inc. ColdFire Module Description CLKIN provides the time base through a programmable prescaler. The UART time scale can also be sourced from a timer input. Full-duplex, auto-echo loopback, local loopback, and remote loopback modes allow testing of UART connections. The programmable UARTs can interrupt the CPU on various normal or error-condition events ...

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... Freescale Semiconductor, Inc. 1.3.8.3 16-Bit Parallel Port Interface A 16-bit general-purpose programmable parallel port serves as either an input or an output on a pin-by-pin basis. 1.3.8.4 Interrupt Controller The interrupt controller provides user-programmable control of ten internal peripheral interrupts and implements four external fixed interrupt-request pins. Each internal interrupt can be programmed to any one of seven interrupt levels and four priority levels within each of these levels ...

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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1.3.10 PLL Module The MCF5407 PLL module is shown in Figure 3. CLKIN DIVIDE[2:0] RSTI The PLL module’s three modes of operation (reset, normal, and reduced power) are described as follows. • Reset mode—When RSTI is asserted, the PLL enters reset mode. At reset, the PLL asserts RSTO from the MCF5407 ...

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... Freescale Semiconductor, Inc. 1.4.1 Programming Model Figure 4 shows the MCF5407 programming model Figure 4. ColdFire MCF5407 Programming Model MOTOROLA MCF5407 Integrated ColdFire® Microprocessor Product Brief For More Information On This Product, Programming Model, Addressing Modes, and Instruction Set 0 D0 Data registers D1 D2 ...

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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set 1.4.2 User Registers The user programming model, shown in Figure 4, is summarized in Table 1. Register Data registers These 32-bit registers are for bit, byte, word, and longword operands. They can also be used as index (D0– ...

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... Freescale Semiconductor, Inc. 1.4.4 Addressing Modes Operands can be signed or unsigned and are contained in registers, memory, or the instructions themselves. The operand specifiers and size for each operation are either explicitly encoded in the instruction or implicitly defined by the instruction’s definition. Table 3 shows MCF5407 data formats. ...

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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set Table 4. Notational Conventions (continued) Instruction #<data> Immediate data following the 16-bit operation word of the instruction <ea> Effective address <ea>y,<ea>x Source and destination effective addresses, respectively <label> Assembly language program label < ...

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... Freescale Semiconductor, Inc. Table 4. Notational Conventions (continued) Instruction {} Optional operation () Identifies an indirect address d Displacement value, n-bits wide (example Address Calculated effective address (pointer) Bit Bit selection (example: Bit 3 of D0) lsb Least significant bit (example: lsb of D0) LSB Least significant byte LSW ...

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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set Table 5. ColdFire Effective Addressing Modes Addressing Modes Syntax Register direct Data Dn Address An Register indirect Address (An) Address with Postincrement (An)+ Address with Predecrement –(An) Address with Displacement (d , An) 16 Address register indirect with scaled index ...

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... Freescale Semiconductor, Inc. Specific Effective Addressing Modes for MOVE Instructions (continued) Table 6. Source <EA> ,Ay,Xi*SF ,PC,Xi*SF) 8 (xxx).W (xxx).L #<data> 1 Note that this applies only to move.b and move.w instructions Table 7 lists additional addressing variants. Addressing Variants Used by Certain Instructions Table 7. Addressing Variant 1 ...

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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set instruction set opcodes, supported operation sizes, and assembler syntax. For two-operand instructions, the first operand in the syntax is generally the source operand, and the second operand is the destination. Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports most of the common 68K opcodes ...

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... Freescale Semiconductor, Inc. describes supervisor-level instructions. Table 9 Table 9. Supervisor-Level Instruction Set Summary Instruction Operand Syntax Operand Size CPUSHL (An) 1 HALT none INTOUCH (Ax) MOVE from SR SR, Dx MOVE to SR Dy,SR #<data>,SR MOVEC Ry,Rc RTE None STOP #<data> WDEBUG <ea-2>y 1 The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE]. ...

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... Freescale Semiconductor, Inc. Programming Model, Addressing Modes, and Instruction Set Table 10. User-Level Instruction Set Summary (continued) Instruction Operand Syntax BCLR Dy,<ea>x .B,.L #<data>,<ea-1>x .B,.L BRA <label> .B,.W,.L BSET Dy,<ea>x .B,.L #<data>,<ea-1>x .B,.L BSR <label> .B,.W,.L BTST Dy,<ea>x .B,.L #<data>,<ea-1>x ...

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... Freescale Semiconductor, Inc. Table 10. User-Level Instruction Set Summary (continued) Instruction Operand Syntax MOVE from MASK,Rx .L MAC ACC,Rx MACSR,Rx MACSR,CCR .L MOVE to Ry,ACC .L MAC Ry,MACSR Ry,MASK #<data>,ACC .L #<data>,MACSR #<data>,MASK MOVE from CCR,Dx .W CCR MOVE to Dy,CCR .B CCR #<data>,CCR MOVEA <ea>y,Ax ...

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... Freescale Semiconductor, Inc. General Device Information Table 10. User-Level Instruction Set Summary (continued) Instruction Operand Syntax SATS Dx .L Scc Dx .B SUB <ea>y,Dx .L Dy,<ea>x .L SUBA <ea>y,Ax .L SUBI #<data>,Dx .L SUBQ #<data>,<ea>x .L SUBX Dy,Dx .L SWAP Dx .W TAS <ea>x .B TRAP #<vector> Unsized TRAPF ...

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... Freescale Semiconductor, Inc. Table 12 lists additional MCF5407 documentation. Documentation Number MCF5407UM/AD MCF5407 User’s Manual TBD Application Note: Migrating from the ColdFire MCF5307 to the MCF5407 MCF5200PRM/AD Rev 1 ColdFire Family Programmer’s Reference Manual MOTOROLA MCF5407 Integrated ColdFire® Microprocessor Product Brief For More Information On This Product, Table 12 ...

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... Freescale Semiconductor, Inc. General Device Information 26 MCF5407 Integrated ColdFire® Microprocessor Product Brief For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

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... Freescale Semiconductor, Inc. MOTOROLA MCF5407 Integrated ColdFire® Microprocessor Product Brief For More Information On This Product, Go to: www.freescale.com General Device Information 27 ...

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... DOCUMENT COMMENTS: FAX (512) 933-2625, Attn: TECD Applications Engineering Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...