MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 2

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Features
2
CLKIN
RAS[1:0]
Addr/Cntrl Mask
RSTI
DACR0/1
peripherals)
PLL Control
DRAM Controller
(to on-chip
DRAM Control
CLKIN
2
PLL
DCR
CAS[3:0]
PLL
Xn
JTAG
DMR0/1
4
PSTCLK
PCLK
RSTO
System Control
SYPCR
MCF5407 Integrated ColdFire® Microprocessor Product Brief
RSR
CSARs CSCRs CSMRs
Chip-Select Module
8
SWIVR
Module
SWSR
Freescale Semiconductor, Inc.
Debug
Local Memory
Instruction Bus
SYSTEM INTEGRATION MODULE (SIM)
÷2
CS[7:0]
For More Information On This Product,
8
8
Figure 1. MCF5407 Block Diagram
Base Address
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8
MBAR
Branch Logic
. .
.
V4 COLDFIRE PROCESSOR COMPLEX
Harvard Cache Controller
8-Entry
Branch
Cache
128-Entry
Prediction
Table
CCR
RAMBAR0 RAMBAR1
Instruction
16-Kbyte
Bus Interface
2-Kbyte
SRAM0
Cache
ACR2
ACR3
32-Bit Data Bus
SRAM Controller
External
32-Bit Address Bus
Bus Master Park
CACR
DIV
MPARK
SRAM1
2-Kbyte
8-Kbyte
OC1
OC2
IAG
Cache
IED
ACR0
ACR1
IC1
IC2
EX
DA
DS
AG
Data
Operand Execution
Pipeline (OEP)
MAC
Instruction Fetch
Pipeline (IFP)
Ten-Instruction
FIFO Buffer
31
Interrupt Controller
12 ICRs
0
Parallel Port
IRQ[1,3,5,7]
4-Entry
Store
Buffer
Local Memory
Data Bus
PLL
4
IRQPAR
AVR
IMR
IPR
Purpose Registers
A0–A7
31
General-
LIFO Return
Stack
0
MOTOROLA
D0–D7
31
Two UARTs
I
Watchdog
2
Channels
Purpose
Software
General-
C Module
Timers
Four
DMA
Two
0