MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 20

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming Model, Addressing Modes, and Instruction Set
instruction set opcodes, supported operation sizes, and assembler syntax. For two-operand instructions, the
first operand in the syntax is generally the source operand, and the second operand is the destination.
Because the ColdFire architecture provides an upgrade path for 68K customers, its instruction set supports
most of the common 68K opcodes. A majority of the instructions are binary compatible or optimized 68K
opcodes. This feature, when coupled with the code conversion tools from third-party developers, generally
minimizes software porting issues for customers with 68K applications.
The following list summarizes new and enhanced instructions of Revision B ISA:
Table 8 lists the new and enhanced instructions.
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New instructions:
— INTOUCH loads blocks of instructions to be locked in the instruction cache
— MOV3Q.L moves 3-bit immediate data to destination location
— MVS.{B,W} sign-extends the source operand and moves it to destination register
— MVZ.{B,W} zero-fills the source operand and moves it to destination register
— SATS.L updates bit 31 of destination register depending on CCR overflow bit
— TAS.B tests and set byte operand being addressed.
Enhancements to existing Revision A instructions:
— Longword support for branch instructions (Bcc, BRA, BSR)
— Byte and word support for compare instructions (CMP, CMPI)
— Byte and longword support for MOVE.x where the source is of type #<data> and the
destination is of type d16(Ax); that is, move.b #<data>, d16(Ax)
Branch Always
Branch Conditionally
Branch to Subroutine
Compare
Compare Immediate
Instruction Fetch Touch
Move 3-Bit Data Quick
Move Data Source to Destination
Move with Sign Extend
Move with Zero-Fill
Signed Saturate
Test and Set an Operand
MCF5407 Integrated ColdFire® Microprocessor Product Brief
Freescale Semiconductor, Inc.
Table 8. ColdFire ISA B Extension Summary
For More Information On This Product,
Instruction
Go to: www.freescale.com
Mnemonic
move.{b,w}
cmpi.{b,w}
cmp.{b,w}
mvs.{b,w}
mvz.{b,w}
mov3q.l
intouch
sats.l
tas.b
bcc.l
bra.l
bsr.l
MOTOROLA