MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 21

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ASL
ASR
Bcc
BCHG
Instruction
1
CPUSHL
HALT
INTOUCH
MOVE from SR
MOVE to SR
MOVEC
RTE
STOP
WDEBUG
Table 9
Table 10
MOTOROLA
The HALT instruction can be configured to allow user-mode execution by setting CSR[UHE].
Instruction
1
describes supervisor-level instructions.
describes user-level instructions.
Dy,<ea>x
<ea>y,Dx
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dy,<ea>x
<ea>y,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
Dy,Dx
#<data>,Dx
<label>
Dy,<ea>x
#<data>,<ea-1>x
Operand Syntax
(An)
none
(Ax)
SR, Dx
Dy,SR
#<data>,SR
Ry,Rc
None
#<data>
<ea-2>y
Operand Syntax Operand Size
MCF5407 Integrated ColdFire® Microprocessor Product Brief
Table 9. Supervisor-Level Instruction Set Summary
Freescale Semiconductor, Inc.
Table 10. User-Level Instruction Set Summary
For More Information On This Product,
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.L
.B,.W,.L
.B,.L
.B,.L
Unsized
Unsized
Unsized
.W
.W
.L
Unsized
.W
.L
Operand Size
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Programming Model, Addressing Modes, and Instruction Set
Invalidate instruction cache line
Push and invalidate data cache line
Push data cache line and invalidate (I,D)-cache lines
Enter halted state
Touch instruction space at address Ax
SR
Source
Ry
Rc
0x002
0x004
0x005
0x006
0x007
0x801
0xC04
0xC05
(SP+2)
Immediate data
<ea-2>y
Source + destination
Source + destination
Immediate data + destination
Immediate data + destination
Source + destination + X
Source & destination
Immediate data & destination
X/C
X/C
MSB
MSB
If condition true, then PC + 2 + d
~(<bit number> of destination)
Bit of destination
Rc
Dx
Register Definition
Cache control register (CACR)
Access control register 0 (ACR0)
Access control register 1 (ACR1)
Access control register 2 (ACR2)
Access control register 3 (ACR3)
Vector base register (VBR)
RAM base address register 0 (RAMBAR0)
RAM base address register 1 (RAMBAR1)
SR; SP+4
SR
debug module
(Dx << Dy)
(Dx << #<data>)
(Dx >> Dy)
(Dx >> #<data>)
SR; enter stopped state
SP; (SP)
Operation
0
X/C
destination
destination
destination
Operation
0
destination
X/C
PC; SP + formatfield
destination
destination
n
destination
Z,
PC
SP
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