MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 8

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ColdFire Module Description
1.3.2
A Harvard memory architecture is implemented to support the increased bandwidth requirements of the V4
processor pipelines. In this design featuring separate instruction and data buses to the processor-local
memories, available bandwidth to the processor reaches 1.3 Gbytes/S at 162 MHz and conflicts between
instruction fetches and operand accesses are removed.
1.3.2.1
Attached to the Harvard memory architecture are a 16-Kbyte instruction cache and an 8-Kbyte data cache.
These four-way, set-associative designs improve system performance by providing pipelined, single-cycle
access on instruction fetches and operand accesses that hit in these memories.
As with all ColdFire caches, these controllers implement a non-lockup, streaming design to maximize
performance. The use of processor-local memories decouples performance from external memory speeds
and increases available bandwidth for external devices or the on-chip 4-channel DMA.
Both caches implement line-fill buffers to optimize the performance of line-sized (16-byte) burst accesses.
Additionally, the data cache supports operation of copyback, write-through or noncacheable modes. A
4-entry, 32-bit buffer is used for cache line push operations and can be configured for deferred write
buffering while in write-through or non-cacheable modes.
The new INTOUCH instruction can be used to prefetch instructions to be locked in the instruction cache
using the cache locking feature. This function may be desirable in certain systems where deterministic
real-time performance is critical.
1.3.2.2
The two 2-Kbyte on-chip SRAM modules are also connected to the Harvard memory architecture, and
provide pipelined, single-cycle access to those memory regions mapped to these devices. Each memory can
be independently mapped to any 0-modulo-2K location within the 4-Gbyte address space, and configured
to respond either to instruction or to data accesses. Time-critical functions can be mapped onto the
instruction memory bus, while the system stack and/or heavily-referenced data operands can be mapped
onto the data memory bus.
1.3.3
The MCF5407 DRAM controller provides a direct interface for up to two blocks of DRAM. The controller
supports 8-, 16-, or 32-bit memory widths, and can easily interface to PC-100 DIMMs. A unique addressing
scheme allows for increases in system memory size without rerouting address lines and rewiring boards.
The controller operates in normal mode or in page mode and supports SDRAMs and EDO DRAMs.
1.3.4
The MCF5407 provides four fully-programmable DMA channels for quick data transfer. Dual- and
single-address modes provide the ability to program bursting and cycle steal. Data transfers are 32 bits long
with packing and unpacking supported along with an auto-alignment option for efficient block transfers.
Automatic block transfers from on-chip serial UARTs are also supported through the DMA channels.
8
Harvard Architecture
DRAM Controller
DMA Controller
16-Kbyte Instruction Cache/8-Kbyte Data Cache
Internal 2-Kbyte SRAMs
MCF5407 Integrated ColdFire® Microprocessor Product Brief
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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