ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 105

• Manufacturer Part Number: ATTINY4-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 6SOT-23
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

14.5.6
14.5.7
14.5.8
14.6
8127D–AVR–02/10
Accessing the Non-Volatile Memory Controller
SLDCS - Serial LoaD data from Control and Status space using direct addressing
SSTCS - Serial STore data to Control and Status space using direct addressing
SKEY - Serial KEY signaling
The SLDCS instruction loads data byte from the TPI Control and Status Space to the TPI physi-
cal layer shift register for serial read-out. The SLDCS instruction uses direct addressing, the
direct address consisting of the 4 address bits of the instruction, as shown in
Table 14-7.
The SSTCS instruction stores the data byte that is shifted into the TPI physical layer shift regis-
ter to the TPI Control and Status Space. The SSTCS instruction uses direct addressing, the
direct address consisting of the 4 address bits of the instruction, as shown in
Table 14-8.
The SKEY instruction is used to signal the activation key that enables NVM programming. The
SKEY instruction is followed by the 8 data bytes that includes the activation key, as shown in
Table
Table 14-9.
By default, NVM programming is not enabled. In order to access the NVM Controller and be able
to program the non-volatile memories, a unique key must be sent using the SKEY instruction.
The 64-bit key that will enable NVM programming is given in
Table 14-10. Enable Key for Non-Volatile Memory Programming
After the key has been given, the Non-Volatile Memory Enable (NVMEN) bit in the TPI Status
Register (TPISR) must be polled until the Non-Volatile memory has been enabled.
NVM programming is disabled by writing a logical zero to the NVMEN bit in TPISR.
Operation
data
Operation
CSS[a]
Operation
Key
Key
NVM Program Enable
←
←
14-9.
←
{8[data}}
CSS[a]
data
The Serial Load Data from Control and Status space (SLDCS) Instruction
The Serial STore data to Control and Status space (SSTCS) Instruction
The Serial KEY signaling (SKEY) Instruction
Opcode
1000 aaaa
Opcode
1100 aaaa
Opcode
1110 0000
Remarks
Bits marked ‘a’ form the direct, 4-bit addres
Remarks
Bits marked ‘a’ form the direct, 4-bit addres
Remarks
Data bytes follow after instruction
Value
0x1289AB45CDD888FF
Table
14-10.
ATtiny4/5/9/10
Table
Table
14-7.
14-8.
105