ATTINY4-TSHR Atmel, ATTINY4-TSHR Datasheet - Page 153

• Manufacturer Part Number: ATTINY4-TSHR
• Description: IC MCU AVR 512B FLASH SOT-23-6
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY4-TSHR

• Package / Case: SOT-23-6
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 12MHz
• Number Of I /o: 4
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Program Memory Size: 512B (512 x 8)
• Oscillator Type: Internal
• Peripherals: POR, PWM, WDT
• Core Size: 8-Bit
• Controller Family/series: ATtiny
• No. Of I/o's: 4
• Ram Memory Size: 32Byte
• Cpu Speed: 12MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 32 B
• Interface Type: ISP
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 4
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 6SOT-23
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 12 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

8127D–AVR–02/10
BCLR
SBI
CBI
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
DATA TRANSFER INSTRUCTIONS
MOV
LDI
LD
LD
LD
LD
LD
LD
LD
LD
LD
LDS
ST
ST
ST
ST
ST
ST
ST
ST
ST
STS
IN
OUT
PUSH
POP
MCU CONTROL INSTRUCTIONS
BREAK
NOP
SLEEP
WDR
Mnemonics
s
A, b
A, b
Rr, b
Rd, b
Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, - X
Rd, Y
Rd, Y+
Rd, - Y
Rd, Z
Rd, Z+
Rd, -Z
Rd, k
X, Rr
X+, Rr
- X, Rr
Y, Rr
Y+, Rr
- Y, Rr
Z, Rr
Z+, Rr
-Z, Rr
k, Rr
Rd, A
A, Rr
Rr
Rd
Operands
Flag Clear
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow.
Clear Two’s Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
Copy Register
Load Immediate
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Load Indirect
Load Indirect and Post-Increment
Load Indirect and Pre-Decrement
Store Direct from SRAM
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment
Store Indirect and Pre-Decrement
Store Indirect
Store Indirect and Post-Increment.
Store Indirect and Pre-Decrement
Store Direct to SRAM
In from I/O Location
Out to I/O Location
Push Register on Stack
Pop Register from Stack
Break
No Operation
Sleep
Watchdog Reset
Description
SREG(s) ← 0
I/O(A, b) ← 1
I/O(A, b) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
C ← 0
N ← 1
N ← 0
Z ← 1
Z ← 0
I ← 1
I ← 0
S ← 1
S ← 0
V ← 1
V ← 0
T ← 1
T ← 0
H ← 1
H ← 0
Rd ← Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Z)
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (k)
(X) ← Rr
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Z) ← Rr
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(k) ← Rr
Rd ← I/O (A)
STACK ← Rr
Rd ← STACK
(see specific descr. for Break)
(see specific descr. for Sleep)
(see specific descr. for WDR)
I/O (A) ← Rr
Operation
ATtiny4/5/9/10
SREG(s)
None
None
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Flags
#Clocks
2/3
2/3
2/3
1/2
1/2
1/2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
1
1
1
2
1
1
2
1
1
2
1
1
1
2
2
1
1
1
1
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