ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 22
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ATTINY10-MAHR
Manufacturer Part Number
ATTINY10-MAHR
Description
MCU AVR 1024K FLASH 12MHZ 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY10-MAHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
ATTINY10-MAH
ATTINY10-MAH
ATTINY10-MAH
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6.5.3
22
ATtiny4/5/9/10
CLKPSR – Clock Prescale Register
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 3:0 – CLKPS[3:0]: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written at run-time to vary the clock frequency and suit the application
requirements. As the prescaler divides the master clock input to the MCU, the speed of all syn-
chronous peripherals is reduced accordingly. The division factors are given in
Table 6-4.
To avoid unintentional changes of clock frequency, a protected change sequence must be fol-
lowed to change the CLKPS bits:
At start-up, CLKPS bits are reset to 0b0011 to select the clock division factor of 8. If the selected
clock source has a frequency higher than the maximum allowed the application software must
make sure a sufficient division factor is used. To make sure the write procedure is not inter-
rupted, interrupts must be disabled when changing prescaler settings.
Bit
0x36
Read/Write
Initial Value
1. Write the signature for change enable of protected I/O register to register CCP
2. Within four instruction cycles, write the desired value to CLKPS bits
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
R
7
–
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
R
5
–
0
CLKPS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R
4
–
0
CLKPS3
R/W
3
0
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLKPS2
R/W
2
0
CLKPS1
R/W
1
1
Clock Division Factor
CLKPS0
8 (default)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
R/W
0
1
128
256
16
32
64
Table
1
2
4
8127D–AVR–02/10
CLKPSR
6-4.
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