ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 83
ATTINY10-MAHR
Manufacturer Part Number
ATTINY10-MAHR
Description
MCU AVR 1024K FLASH 12MHZ 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY10-MAHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
ATTINY10-MAH
ATTINY10-MAH
ATTINY10-MAH
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12.1.2
8127D–AVR–02/10
DIDR0 – Digital Input Disable Register 0
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one, the Analog Comparator interrupt request is enabled.
When written logic zero, the interrupt request is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When set, this bit enables the input capture function in Timer/Counter0 to be triggered by the
analog comparator. In this case, the comparator output is directly connected to the input capture
front-end logic, using the noise canceler and edge select features of the Timer/Counter0 input
capture interrupt. To make the comparator trigger the Timer/Counter0 input capture interrupt,
the ICIE1 bit in “TIMSK0 – Timer/Counter Interrupt Mask Register 0” must be set.
When this bit is cleared, no connection between the analog comparator and the input capture
function exists.
• Bits 1:0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the analog comparator interrupt. The
different settings are shown in
Table 12-1.
When changing the ACIS1/ACIS0 bits, the analog comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in “ACSR – Analog Comparator Control and Status Register”.
Otherwise an interrupt can occur when the bits are changed.
• Bits 1:0 – ADC1D, ADC0D: Digital Input Disable
When this bit is set, the digital input buffer on pin AIN1 (ADC1) / AIN0 (ADC0) is disabled and
the corresponding PIN register bit will read as zero. When used as an analog input but not
required as a digital input the power consumption in the digital input buffer can be reduced by
writing this bit to logic one.
Bit
0x17
Read/Write
Initial Value
ACIS1
0
0
1
1
Selecting Source for Analog Comparator Interrupt.
R
7
–
0
ACIS0
0
1
0
1
R
6
–
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
R
5
–
0
12-1.
4
–
R
0
R
3
–
0
R
2
–
0
ADC1D
R/W
1
0
ATtiny4/5/9/10
ADC0D
R/W
0
0
DIDR0
83
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