ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 80
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ATTINY10-MAHR
Manufacturer Part Number
ATTINY10-MAHR
Description
MCU AVR 1024K FLASH 12MHZ 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY10-MAHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
ATTINY10-MAH
ATTINY10-MAH
ATTINY10-MAH
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11.11.9
11.11.10 GTCCR – General Timer/Counter Control Register
80
ATtiny4/5/9/10
TIFR0 – Timer/Counter Interrupt Flag Register 0
• Bits 7:6, 4:3 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when the register is written.
• Bit 5 – ICF0: Timer/Counter0, Input Capture Flag
This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register
(ICR0) is set by the WGM03:0 to be used as the TOP value, the ICF0 flag is set when the coun-
ter reaches the TOP value.
ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF0 can be cleared by writing a logic one to its bit location.
• Bit 2 – OCF1B: Timer/Counter0, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output
Compare Register B (OCR0B).
Note that a Forced Output Compare (0B) strobe will not set the OCF0B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF0A: Timer/Counter0, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT0) value matches the Output
Compare Register A (OCR0A).
Note that a Forced Output Compare (1A) strobe will not set the OCF0A flag.
OCF0A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF0A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV0: Timer/Counter0, Overflow Flag
The setting of this flag is dependent of the WGM03:0 bits setting. In Normal and CTC modes,
the TOV0 flag is set when the timer overflows. See
behavior when using another WGM03:0 bit setting.
TOV0 is automatically cleared when the Timer/Counter0 Overflow Interrupt Vector is executed.
Alternatively, TOV0 can be cleared by writing a logic one to its bit location.
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSR bit is kept, hence keeping the Prescaler Reset signal asserted.
Bit
0x2A
Read/Write
Initial Value
Bit
0x2F
Read/Write
Initial Value
TSM
R/W
7
0
R
7
–
0
R
R
6
–
0
6
–
0
ICF0
R/W
5
0
R
5
–
0
R
4
–
0
R
4
–
0
R
3
–
0
Table 11-5 on page 76
R
3
–
0
OCF0B
R/W
2
0
R
2
–
0
OCF0A
R/W
1
0
R
1
–
0
for the TOV0 flag
TOV0
R/W
PSR
0
0
R/W
0
0
8127D–AVR–02/10
TIFR0
GTCCR
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