ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 27

• Manufacturer Part Number: ATTINY10-MAHR
• Description: MCU AVR 1024K FLASH 12MHZ 8UDFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY10-MAHR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 12MHz
• Peripherals: POR, PWM, WDT
• Number Of I /o: 4
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Ram Size: 32 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: ATTINY10-MAH; ATTINY10-MAH

8. System Control and Reset
8.1
8.2
8127D–AVR–02/10
Resetting the AVR
Reset Sources
During reset, all I/O registers are set to their initial values, and the program starts execution from
the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative Jump –
instruction to the reset handling routine. If the program never enables an interrupt source, the
interrupt vectors are not used, and regular program code can be placed at these locations. The
circuit diagram in
defined in section
Figure 8-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The start up
sequence is described in
The ATtiny4/5/9/10 have three sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the
threshold (V
than the minimum pulse length
Watchdog is enabled
Pull-up Resistor
Reset Logic
POT
Figure 8-1
FILTER
SPIKE
“System and Reset Characteristics” on page
)
“Starting from Reset” on page
shows the reset logic. Electrical parameters of the reset circuitry are
Power-on Reset
Watchdog
Oscillator
Generator
Circuit
Clock
CK
Reset Flag Register
DATA BUS
(RSTFLR)
Delay Counters
20.
120.
ATtiny4/5/9/10
TIMEOUT
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