ATTINY10-MAHR Atmel, ATTINY10-MAHR Datasheet - Page 32
ATTINY10-MAHR
Manufacturer Part Number
ATTINY10-MAHR
Description
MCU AVR 1024K FLASH 12MHZ 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY10-MAHR
Core Processor
AVR
Core Size
8-Bit
Speed
12MHz
Peripherals
POR, PWM, WDT
Number Of I /o
4
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Ram Size
32 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Other names
ATTINY10-MAH
ATTINY10-MAH
ATTINY10-MAH
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8.3.2
8.4
8.4.1
32
Register Description
ATtiny4/5/9/10
Code Examples
WDTCSR – Watchdog Timer Control and Status Register
The following code example shows how to turn off the WDT. The example assumes that inter-
rupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during
execution of these functions.
Note:
• Bit 7 – WDIF: Watchdog Timer Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-
ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the WDIE
is set, the Watchdog Time-out Interrupt is requested.
• Bit 6 – WDIE: Watchdog Timer Interrupt Enable
When this bit is written to one, the Watchdog interrupt request is enabled. If WDE is cleared in
combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding
interrupt is requested if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Bit
0x31
Read/Write
Initial Value
Assembly Code Example
WDT_off:
wdr
; Clear WDRF in RSTFLR
in
andi
out
; Write signature for change enable of protected I/O register
ldi r16, 0xD8
out CCP, r16
; Within four instruction cycles, turn off WDT
ldi r16, (0<<WDE)
out WDTCSR, r16
ret
See
“Code Examples” on page
r16, RSTFLR
RSTFLR, r16
WDIF
r16, ~(1<<WDRF)
R/W
7
0
WDIE
R/W
6
0
WDP3
R/W
5
0
5.
R
4
–
0
WDE
R/W
3
X
WDP2
R/W
2
0
WDP1
R/W
1
0
WDP0
R/W
0
0
WDTCSR
8127D–AVR–02/10
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