PIC16LF1827-I/SO Microchip Technology, PIC16LF1827-I/SO Datasheet - Page 311

• Manufacturer Part Number: PIC16LF1827-I/SO
• Description: IC MCU 8BIT 4KB FLASH 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1827-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

FIGURE 25-12:
TABLE 25-8:
© 2009 Microchip Technology Inc.
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
SPBRGL
SPBRGH
TRISB
TXSTA
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
Note:
TX/CK pin
TX/CK pin
CREN bit
SREN bit
bit SREN
RCIF bit
RCREG
Name
RX/DT
Write to
Read
pin
*
Page provides register information.
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
‘0’
EUSART Receive Data Register
Baud Rate Generator Data Register Low
Baud Rate Generator Data Register High
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
CSRC
SPEN
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER
RECEPTION
GIE
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TRISB6
bit 0
RCIDL
ADIE
PEIE
ADIF
Bit 6
RX9
TX9
bit 1
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
bit 2
TRISB4
Preliminary
CREN
SCKP
SYNC
INTE
Bit 4
TXIE
TXIF
bit 3
SSP1IE
SSP1IF
ADDEN
TRISB3
SENDB
BRG16
IOCIE
Bit 3
bit 4
PIC16F/LF1826/27
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
Bit 2
—
bit 5
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
Bit 1
INTF
bit 6
TMR1IE
TMR1IF
ABDEN
TRISB0
bit 7
IOCIF
RX9D
TX9D
Bit 0
DS41391B-page 311
Register
on Page
292*
299*
299*
298
297
126
296
89
90
94
‘0’