PIC16F688-I/ML Microchip Technology, PIC16F688-I/ML Datasheet - Page 294

• Manufacturer Part Number: PIC16F688-I/ML
• Description: IC PIC MCU FLASH 4KX14 16QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 16-QFN
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART/RS- 232/SCI/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
17.4
DS31017A-page 17-18
SSP I
2
C™ Operation
The MSSP module in I
eral call support) and provides interrupts on start and stop bits in hardware to determine a free
bus (multi-master function). The SSP module implements the standard mode specifications as
well as 7-bit and 10-bit addressing.
A “glitch” filter is on the SCL and SDA pins when the pin is an input. This filter operates in both
the 100 KHz and 400 KHz modes. In the 100 KHz mode, when these pins are an output, there
is a slew rate control of the pin that is independent of device frequency.
Figure 17-10: I
Figure 17-11: I
2
2
C Slave Mode Block Diagram
C Master Mode Block Diagram
SDA
SDA
SCL
Baud Rate Generator
2
SCL
SSPADD<6:0>
C mode fully implements all master and slave functions (including gen-
Preliminary
7
Read
Read
Appendix A
clock
clock
shift
shift
MSb
MSb
Start and Stop bit
detect / generate
Stop bit detect
Match detect
SSPBUF reg
Match detect
SSPADD reg
SSPBUF reg
SSPADD reg
SSPSR reg
SSPSR reg
Start and
gives an overview of the I
LSb
LSb
Write
Write
data bus
data bus
Internal
Internal
(SSPSTAT reg)
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
Clear/Set P bit
Address Match
Address Match
Set, Reset
S, P bits
and
1997 Microchip Technology Inc.
2
C bus specification.