PIC16F688-I/ML Microchip Technology, PIC16F688-I/ML Datasheet - Page 394
![IC PIC MCU FLASH 4KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F688-I/ML
Manufacturer Part Number
PIC16F688-I/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-IML.pdf
(202 pages)
Specifications of PIC16F688-I/ML
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
16-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART/RS- 232/SCI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- PIC16F688-IML PDF datasheet #6
- Current page: 394 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
21.7
DS31021A-page 21-10
A/D Conversions
Example 21-2
inputs. The analog reference (V
conversion clock is F
Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES
register will NOT be updated with the partially completed A/D conversion sample. That is, the
ADRES register will continue to contain the value of the last completed conversion (or the last
value written to the ADRES register). After the A/D conversion is aborted, a 2T
before the next acquisition is started. After this 2T
on the selected channel.
Example 21-2:
Figure 21-4: A/D Conversion T
;
;
;
;
Note:
Ensure that the required sampling time for the selected input
channel has elapsed. Then the conversion may be started.
BSF
CLRF
BSF
BCF
MOVLW
MOVWF
BCF
BSF
BSF
BSF
Set GO bit
T
:
:
:
AD
1 T
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D,
due to the required acquition time requirement.
Holding capacitor is disconnected
from analog input
show how to perform an A/D conversion. The I/O pins are configured as analog
STATUS, RP0
ADCON1
PIE1,
STATUS, RP0
0xC1
ADCON0
PIR1,
INTCON, PEIE
INTCON, GIE
ADCON0, GO
AD
b7
Doing an A/D Conversion
2 T
RC
. The conversion is performed on the AN0 channel.
AD
b6
ADIE
ADIF
3 T
AD
b5
REF
AD
4 T
) is the device V
Cycles
; Select Bank1
; Configure A/D inputs
; Enable A/D interrupts
; Select Bank0
; RC Clock, A/D is on, Channel 0 is selected
;
; Clear A/D interrupt flag bit
; Enable peripheral interrupts
; Enable all interrupts
; Start A/D Conversion
; The ADIF bit will be set and the GO/DONE
; bit is cleared upon completion of the
;
b4
AD
5 T
A/D Conversion.
Holding capacitor is connected to analog input
b3
AD
6 T
AD
DD
wait, an acquisition is automatically started
. The A/D interrupt is enabled, and the A/D
b2
AD
Next Q4: ADRES is loaded
7 T
AD
b1
8 T
GO bit is cleared
ADIF bit is set
1997 Microchip Technology Inc.
AD
b0
9 T
AD
b0
AD
10
wait is required
T
AD
11
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