PIC16F688-I/ML Microchip Technology, PIC16F688-I/ML Datasheet - Page 56
![IC PIC MCU FLASH 4KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F688-I/ML
Manufacturer Part Number
PIC16F688-I/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-IML.pdf
(202 pages)
Specifications of PIC16F688-I/ML
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
16-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART/RS- 232/SCI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- PIC16F688-IML PDF datasheet #6
- Current page: 56 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
3.2.4
DS31003A-page 3-6
INTERNAL RESET
PWRT TIME-OUT
INTERNAL POR
OST TIME-OUT
Power-up Sequence
MCLR
V
DD
Note 1: Devices with the Internal/External RC option have a nominal 250 s delay.
On power-up, the time-out sequence is as follows: First the internal POR is detected, then, if
enabled, the PWRT time-out is invoked. After the PWRT time-out is over, the OST is activated.
The total time-out will vary based on oscillator configuration and PWRTE bit status. For example,
in RC mode with the PWRTE bit set (PWRT disabled), there will be no time-out at all.
Figure 3-6
Since the time-outs occur from the internal POR pulse, if MCLR is kept low long enough, the
time-outs will expire. Then bringing MCLR high will begin execution immediately
This is useful for testing purposes or to synchronize more than one device operating in parallel.
If the device voltage is not within the electrical specifications by the end of a time-out, the
MCLR/V
external RC delay is sufficient for many of these applications.
Table 3-1
Figure 3-8
Table 3-1:
Figure 3-5: Time-out Sequence on Power-up (MCLR Tied to V
Configuration
XT, HS, LP
Oscillator
RC
PP
shows the time-outs that occur in various situations, while
and
show four different cases that can happen on powering up the device.
pin must be held low until the voltage is within the device specification. The use of an
Time-out in Various Situations
Figure 3-7
72 ms + 1024T
Enabled
72 ms
depict time-out sequences.
Power-up Timer
T
PWRT
OSC
1024T
Disabled
T
OST
—
(1)
OSC
72 ms + 1024T
Brown-out Reset
72 ms
DD
1997 Microchip Technology Inc.
)
OSC
Figure 3-5
(Figure
1024T
Wake-up
Figure
SLEEP
from
—
through
(1)
OSC
3-7).
3-5,
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