PIC16F688-I/ML Microchip Technology, PIC16F688-I/ML Datasheet - Page 389
![IC PIC MCU FLASH 4KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F688-I/ML
Manufacturer Part Number
PIC16F688-I/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-IML.pdf
(202 pages)
Specifications of PIC16F688-I/ML
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
16-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART/RS- 232/SCI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- PIC16F688-IML PDF datasheet #6
- Current page: 389 of 688
- Download datasheet (3Mb)
21.3
1997 Microchip Technology Inc.
Operation
When the A/D conversion is complete, the result is loaded into the ADRES register, the
GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit, ADIF, is set.
After the A/D module has been configured as desired, the selected channel must be acquired
before the conversion is started. The analog input channels must have their corresponding TRIS
bits selected as an input. To determine acquisition time, see Subsection
Requirements.”
following steps should be followed for doing an A/D conversion:
1.
2.
3.
4.
5.
6.
7.
Figure 21-2
time that the A/D module’s holding capacitor is connected to the external voltage level. Then
there is the conversion time of 10 T
two times is the sampling time. There is a minimum acquisition time to ensure that the holding
capacitor is charged to a level that will give the desired accuracy for the A/D conversion.
Figure 21-2: A/D Conversion Sequence
Configure the A/D module:
• Configure analog pins / voltage reference / and digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear the ADIF bit
• Set the ADIE bit
• Set the GIE bit
Wait the required acquisition time.
Start conversion:
• Set the GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear the ADIF bit, if required.
For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is
defined as T
When A/D holding capacitor start to charge.
After A/D conversion, or new A/D channel is selected.
Acquisition Time
shows the conversion sequence, and the terms that are used. Acquisition time is the
Section 21. 8-bit A/D Converter
AD
After this acquisition time has elapsed the A/D conversion can be started. The
. A minimum wait of 2T
A/D Sample Time
When A/D conversion is started (setting the GO bit).
Holding capacitor is disconnected from the analog input before
the conversion is started.
Conversion Time
AD
, which is started when the GO bit is set. The sum of these
AD
is required before next acquisition starts.
A/D conversion complete,
result is loaded in ADRES register.
Holding capacitor begins acquiring
voltage level on selected channel.
ADIF bit is set.
21.4 “A/D Acquisition
DS31021A-page 21-5
21
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