PIC16F688-I/ML Microchip Technology, PIC16F688-I/ML Datasheet - Page 320
![IC PIC MCU FLASH 4KX14 16QFN](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F688-I/ML
Manufacturer Part Number
PIC16F688-I/ML
Description
IC PIC MCU FLASH 4KX14 16QFN
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(204 pages)
3.PIC16F688T-ISL.pdf
(6 pages)
4.PIC16F688T-ISL.pdf
(4 pages)
5.PIC16F688T-ISL.pdf
(688 pages)
6.PIC16F688-IML.pdf
(202 pages)
Specifications of PIC16F688-I/ML
Program Memory Type
FLASH
Program Memory Size
7KB (4K x 14)
Package / Case
16-QFN
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART/RS- 232/SCI/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFNAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F688T-ISL PDF datasheet #3
- PIC16F688T-ISL PDF datasheet #4
- PIC16F688T-ISL PDF datasheet #5
- PIC16F688-IML PDF datasheet #6
- Current page: 320 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.4.13
17.4.13.1 WCOL Status Flag
DS31017A-page 17-44
Acknowledge Sequence Timing
An acknowledge sequence is enabled by setting the acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the acknowl-
edge data bit is presented on the SDA pin. If the user wishes to generate an acknowledge, then
the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an
acknowledge sequence. The baud rate generator then counts for one rollover period (T
the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for T
ACKEN bit is automatically cleared, the baud rate generator is turned off, and the SSP module
then goes into IDLE mode
If the user writes the SSPBUF when an acknowledge sequence is in progress, then WCOL is set
and the contents of the buffer are unchanged (the write doesn’t occur).
Figure 17-29: Acknowledge Sequence Waveform
SSPIF
Acknowledge sequence starts here,
SDA
SCL
Note: T
Set SSPIF at the end
of receive
BRG
= one baud rate generator period.
ACKEN = 1, ACKDT = 0
Write to SSPCON2
(Figure
Preliminary
8
D0
17-29).
BRG
. The SCL pin is then pulled low. Following this, the
Cleared in
software
T
BRG
ACK
T
BRG
9
Set SSPIF at the end
of acknowledge sequence
ACKEN automatically cleared
1997 Microchip Technology Inc.
Cleared in
software
BRG
), and
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