ATMEGA8535-16MU Atmel, ATMEGA8535-16MU Datasheet - Page 101

• Manufacturer Part Number: ATMEGA8535-16MU
• Description: IC AVR MCU 8K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Modes of Operation
Normal Mode
Clear Timer on Compare
Match (CTC) Mode
2502K–AVR–10/06
A change of the COM1x1:0 bits state will have effect at the first Compare Match after
the bits are written. For non-PWM modes, the action can be forced to have immediate
effect by using the FOC1x strobe bits.
The mode of operation, i.e., the behavior of the Timer/Counter and the output compare
pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and
Compare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affect
the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0
bits control whether the PWM output generated should be inverted or not (inverted or
non-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the out-
put should be set, cleared or toggle at a Compare Match (See “Compare Match Output
Unit” on page 100.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 108.
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the
counting direction is always up (incrementing), and no counter clear is performed. The
counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and
then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Over-
flow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.
The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared.
However, combined with the timer overflow interrupt that automatically clears the TOV1
Flag, the timer resolution can be increased by software. There are no special cases to
consider in the Normal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maxi-
mum interval between the external events must not exceed the resolution of the counter.
If the interval between events are too long, the timer overflow interrupt or the prescaler
must be used to extend the resolution for the capture unit.
The output compare units can be used to generate interrupts at some given time. Using
the output compare to generate waveforms in normal mode is not recommended, since
this will occupy too much of the CPU time.
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1
Register is used to manipulate the counter resolution. In CTC mode the counter is
cleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0
= 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for the
counter, hence also its resolution. This mode allows greater control of the Compare
Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 45. The counter value
(TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and then
counter (TCNT1) is cleared.
ATmega8535(L)
101