ATMEGA8535-16MU Atmel, ATMEGA8535-16MU Datasheet - Page 120

• Manufacturer Part Number: ATMEGA8535-16MU
• Description: IC AVR MCU 8K 16MHZ 5V 44-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8535-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-VQFN Exposed Pad
• Processor Series: ATMEGA8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 44MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Force Output Compare
Compare Match Blocking by
TCNT2 Write
Using the Output Compare
Unit
120
ATmega8535(L)
Figure 55. Output Compare Unit, Block Diagram
The OCR2 Register is double buffered when using any of the pulse width modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR2 Compare Register to either top or bottom of the counting sequence. The synchro-
nization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
The OCR2 Register access may seem complex, but this is not the case. When the dou-
ble buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double
buffering is disabled the CPU will access the OCR2 directly.
In non-PWM waveform generation modes, the match output of the comparator can be
forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare
Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be
updated as if a real Compare Match had occurred (the COM21:0 bits settings define
whether the OC2 pin is set, cleared or toggled).
All CPU write operations to the TCNT2 Register will block any Compare Match that
occurs in the next timer clock cycle, even when the timer is stopped. This feature allows
OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when
the Timer/Counter clock is enabled.
Since writing TCNT2 in any mode of operation will block all compare matches for one
timer clock cycle, there are risks involved when changing TCNT2 when using the output
compare channel, independently of whether the Timer/Counter is running or not. If the
value written to TCNT2 equals the OCR2 value, the Compare Match will be missed,
resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value
equal to BOTTOM when the counter is down-counting.
The setup of the OC2 should be performed before setting the Data Direction Register for
the port pin to output. The easiest way of setting the OC2 value is to use the force output
compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even
when changing between Waveform Generation modes.
bottom
FOCn
top
OCRn
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMn1:0
TCNTn
OCFn (Int.Req.)
OCxy
2502K–AVR–10/06