ATMEGA8535-16MU Atmel, ATMEGA8535-16MU Datasheet - Page 54

IC AVR MCU 8K 16MHZ 5V 44-QFN

ATMEGA8535-16MU

Manufacturer Part Number
ATMEGA8535-16MU
Description
IC AVR MCU 8K 16MHZ 5V 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8535-16MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
4.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44MLF EP
Device Core
AVR
Family Name
ATmega
Maximum Speed
16 MHz
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8535-16MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
54
ATmega8535(L)
ceeding positive clock edge. As indicated by the two arrows t
signal transition on the pin will be delayed between ½ and 1½ system clock period
depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as
indicated in Figure 25. The out instruction sets the “SYNC LATCH” signal at the positive
edge of the clock. In this case, the delay t
clock period.
Figure 25. Synchronization when Reading a Software Assigned Pin Value
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
PINxn
r16
r17
out PORTx, r16
pd
0x00
through the synchronizer is one system
nop
t
pd
0xFF
in r17, PINx
pd,max
and t
pd,min
2502K–AVR–10/06
, a single
0xFF

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