ATTINY2313-20SU Atmel, ATTINY2313-20SU Datasheet - Page 144

• Manufacturer Part Number: ATTINY2313-20SU
• Description: IC MCU AVR 2K FLASH 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313-20SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/USART/USI
• Total Internal Ram Size: 128Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: SOIC
• Package: 20SOIC
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Processor Series: ATTINY2x
• Core: AVR8
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Data Rom Size: 128 B
• Height: 2.35 mm
• Length: 13 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.6 mm
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Compliant

Start Condition
Detector
Alternative USI
Usage
Half-duplex
Asynchronous Data
Transfer
4-bit Counter
12-bit Timer/Counter
Edge Triggered
External Interrupt
Software Interrupt
USI Register
Descriptions
USI Data Register –
USIDR
144
ATtiny2313
The start condition detector is shown in Figure 65. The SDA line is delayed (in the range of 50 to
300 ns) to ensure valid sampling of the SCL line.
The start condition detector is working asynchronously and can therefore wake up the processor
from the Power-down sleep mode. However, the protocol used might have restrictions on the
SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time set by
the CKSEL Fuses (see
into the consideration.
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
By utilizing the Shift Register in Three-wire mode, it is possible to implement a more compact
and higher performance UART than by software only.
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The overflow flag and interrupt enable bit are then used for the external interrupt. This feature is
selected by the USICS1 bit.
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
The USI uses no buffering of the serial register, i.e., when accessing the Data Register (USIDR)
the serial register is accessed directly. If a serial clock occurs at the same cycle the register is
written, the register will contain the value written and no shift is performed. A (left) shift operation
is performed depending of the USICS1..0 bits setting. The shift operation can be controlled by
an external clock edge, by a Timer/Counter0 overflow, or directly by software using the USICLK
strobe bit. Note that even when no wire mode is selected (USIWM1..0 = 0) both the external
data input (DI/SDA) and the external clock input (USCK/SCL) can still be used by the Shift
Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch
to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) dur-
ing the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1),
and constantly open when an internal clock source is used (USICS1 = 0). The output will be
changed immediately when a new MSB written as long as the latch is open. The latch ensures
that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register to the pin must be set to one for enabling
data output from the Shift Register.
Bit
Read/Write
Initial Value
MSB
R/W
7
0
R/W
“Clock Systems and their Distribution” on page
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
22) must also be taken
LSB
R/W
0
0
USIDR
2543L–AVR–08/10