PIC16F627A-I/SS Microchip Technology, PIC16F627A-I/SS Datasheet - Page 108
![IC MCU FLASH 1KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F627A-I/SS
Manufacturer Part Number
PIC16F627A-I/SS
Description
IC MCU FLASH 1KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
5.PIC16F627A-ISO.pdf
(168 pages)
6.PIC16F648A-ISS.pdf
(178 pages)
Specifications of PIC16F627A-I/SS
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Package
20SSOP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPI3DBF648 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F627A-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC16F627A/628A/648A
TABLE 14-8:
14.6
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
Status Register). This must be implemented in
software.
Example 14-2 stores and restores the Status and W
registers. The user register, W_TEMP, must be defined
in a common memory location (i.e., W_TEMP is
defined at 0x70 in Bank 0 and is therefore, accessible
at 0xF0, 0x170 and 0x1F0). The Example 14-2:
• Stores the W register
• Stores the Status Register
• Executes the ISR code
• Restores the Status (and bank select bit register)
• Restores the W register
EXAMPLE 14-2:
DS40044B-page 106
10Bh, 18Bh
MOVWF W_TEMP
SWAPF STATUS,W
BCF
MOVWF STATUS_TEMP ;save status to bank 0
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register
MOVWF STATUS
SWAPF W_TEMP,F
SWAPF W_TEMP,W
0Bh, 8Bh,
Address
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal
0Ch
8Ch
:
:(ISR)
:
STATUS,RP0
Context Saving During Interrupts
operation.
INTCON
Name
PIR1
PIE1
SUMMARY OF INTERRUPT REGISTERS
;copy W to temp register,
;could be in any bank
;swap status to be saved
;into W
;change to bank 0
;regardless of current
;bank
;register
;into W, sets bank to original
;state
;move W into STATUS register
;swap W_TEMP
;swap W_TEMP into W
SAVING THE STATUS
AND W REGISTERS IN
RAM
EEIF
EEIE
Bit 7
GIE
CMIE
CMIF
Bit 6
PEIE
RCIF
RCIE
Bit 5
T0IE
INTE
Bit 4
TXIF
TXIE
Preliminary
RBIE
Bit 3
—
—
14.7
The watchdog timer is a free running on-chip RC
oscillator which does not require any external
components. This RC oscillator is separate from the
RC oscillator of the CLKIN pin. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped, for example, by
execution of a
ation, a WDT time out generates a device Reset. If the
device is in Sleep mode, a WDT time out causes the
device to wake-up and continue with normal operation.
The WDT can be permanently disabled by program-
ming
(Section 14.1 "Configuration Bits").
14.7.1
The WDT has a nominal time out period of 18 ms (with
no prescaler). The time out periods vary with tempera-
ture, V
DC Specifications, Table 17-7). If longer time out
periods are desired, a postscaler with a division ratio of
up to 1:128 can be assigned to the WDT under
software control by writing to the OPTION register.
Thus, time out periods up to 2.3 seconds can be
realized.
The
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the Status Register will be cleared upon a
Watchdog Timer time out.
14.7.2
It should also be taken in account that under worst case
conditions (V
WDT prescaler) it may take several seconds before a
WDT time out occurs.
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
Bit 2
T0IF
CLRWDT
DD
the
Watchdog Timer (WDT)
and process variations from part to part (see
Bit 1
INTF
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
DD
configuration
and
SLEEP
= Min., Temperature = Max., max.
SLEEP
Bit 0
RBIF
instruction. During normal oper-
2004 Microchip Technology Inc.
instructions clear the WDT
0000 000x
0000 -000
0000 -000
POR Reset
bit
Value on
WDTE
Value on all
0000 000u
0000 -000
0000 -000
Resets
as
other
clear
(1)