PIC16F627A-I/SS Microchip Technology, PIC16F627A-I/SS Datasheet - Page 99
![IC MCU FLASH 1KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F627A-I/SS
Manufacturer Part Number
PIC16F627A-I/SS
Description
IC MCU FLASH 1KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
5.PIC16F627A-ISO.pdf
(168 pages)
6.PIC16F648A-ISS.pdf
(178 pages)
Specifications of PIC16F627A-I/SS
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
20-SSOP
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Package
20SSOP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPI3DBF648 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F627A-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
14.2.8
A software programmable dual speed Oscillator mode
is provided when the PIC16F627A/628A/648A is
configured in the INTOSC Oscillator mode. This feature
allows users to dynamically toggle the oscillator speed
between 4 MHz and 37 kHz nominal in the INTOSC
mode. Applications that require low current power
savings, but cannot tolerate putting the part into Sleep,
may use this mode.
There is a time delay associated with the transition
between Fast and Slow oscillator speeds. This
Oscillator Speed Transition delay consists of two
existing clock pulses and eight new speed clock
pulses. During this Clock Speed Transition Delay the
System Clock is halted causing the processor to be
frozen in time. During this delay the Program Counter
and the Clock Out stop.
The OSCF bit in the PCON register is used to control Dual
Speed mode. See Section 4.2.2.6 "PCON Register",
Register 4-6.
FIGURE 14-6:
2004 Microchip Technology Inc.
Note
V
MCLR/
OSC1/
CLKIN
PP
V
Pin
DD
Pin
1:
On-chip
SPECIAL FEATURE: DUAL SPEED
OSCILLATOR MODES
This is a separate oscillator from the INTOSC/RC oscillator.
OSC
OST/PWRT
detect Reset
Brown-out
V
(1)
Module
detect
WDT
DD
Schmitt Trigger Input
rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Time out
Reset
Power-on Reset
WDT
10-bit Ripple-counter
10-bit Ripple-counter
BOREN
External
Reset
Sleep
Preliminary
Enable PWRT
Enable OST
PIC16F627A/628A/648A
14.3
The PIC16F627A/628A/648A differentiates between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
Some registers are not affected in any Reset condition;
their status is unknown on POR and unchanged in any
other Reset. Most other registers are reset to a “Reset
state” on Power-on Reset, Brown-out Reset, MCLR
Reset, WDT Reset and MCLR Reset during Sleep.
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different Reset
situations as indicated in Table 14-4. These bits are
used in software to determine the nature of the Reset.
See Table 14-7 for a full description of Reset states of
all registers.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 14-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 17-7 for pulse width
specification.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset (normal operation)
WDT wake-up (Sleep)
Brown-out Reset (BOR)
See Table 14-3 for time out situations.
Reset
S
R
DS40044B-page 97
Q
Q
Chip_Reset