PIC18F45J10-E/P Microchip Technology, PIC18F45J10-E/P Datasheet - Page 164
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F45J10-E/P
Manufacturer Part Number
PIC18F45J10-E/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 164 of 368
- Download datasheet (6Mb)
PIC18F45J10 FAMILY
REGISTER 16-5:
DS39682E-page 162
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
GCEN
R/W-0
2:
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive.
If the I
(or writes to the SSPxBUF are disabled).
GCEN: General Call Enable bit
Unused in Master mode.
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (Master Receive mode only)
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
0 = Acknowledge sequence Idle
RCEN: Receive Enable bit (Master Receive mode only)
1 = Enables Receive mode for I
0 = Receive Idle
PEN: Stop Condition Enable bit
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
RSEN: Repeated Start Condition Enable bit
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
SEN: Start Condition Enable bit
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
ACKSTAT
2
R/W-0
C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
Automatically cleared by hardware.
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
W = Writable bit
‘1’ = Bit is set
ACKDT
R/W-0
(1)
ACKEN
(2)
(2)
2
C
R/W-0
(2)
(2)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
RCEN
R/W-0
(2)
(2)
(1)
2
PEN
R/W-0
C™ MASTER MODE)
(2)
© 2009 Microchip Technology Inc.
x = Bit is unknown
RSEN
R/W-0
(2)
SEN
R/W-0
(2)
bit 0
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