PIC18F45J10-E/P Microchip Technology, PIC18F45J10-E/P Datasheet - Page 93
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F45J10-E/P
Manufacturer Part Number
PIC18F45J10-E/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
Specifications of PIC18F45J10-E/P
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- Current page: 93 of 368
- Download datasheet (6Mb)
REGISTER 9-8:
REGISTER 9-9:
© 2009 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-4
bit 3
bit 2-1
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-0
OSCFIE
SSP2IE
R/W-0
R/W-0
OSCFIE: Oscillator Fail Interrupt Enable bit
1 = Enabled
0 = Disabled
CMIE: Comparator Interrupt Enable bit
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module)
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
CCP2IE: CCP2 Interrupt Enable bit
1 = Enabled
0 = Disabled
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
Unimplemented: Read as ‘0’
BCL2IE
R/W-0
R/W-0
CMIE
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
W = Writable bit
W = Writable bit
‘1’ = Bit is set
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC18F45J10 FAMILY
BCL1IE
R/W-0
U-0
—
U-0
U-0
—
—
x = Bit is unknown
x = Bit is unknown
U-0
U-0
—
—
DS39682E-page 91
CCP2IE
R/W-0
U-0
—
bit 0
bit 0
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