PIC18F45J10-E/P Microchip Technology, PIC18F45J10-E/P Datasheet - Page 39

• Manufacturer Part Number: PIC18F45J10-E/P
• Description: IC PIC MCU FLASH 16KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.2.3
In RC_RUN mode, the CPU and peripherals are
clocked from the internal oscillator; the primary clock is
shut down. This mode provides the best power conser-
vation of all the Run modes, while still executing code.
It works well for user applications which are not highly
timing-sensitive or do not require high-speed clocks at
all times.
This mode is entered by setting SCS<1:0> to ‘11’.
When the clock source is switched to the INTRC (see
Figure 4-2), the primary oscillator is shut down and the
OSTS bit is cleared.
FIGURE 4-2:
FIGURE 4-3:
© 2009 Microchip Technology Inc.
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
Note 1: T
RC_RUN MODE
CPU Clock
CPU
Peripheral
Program
Counter
INTRC
OSC1
Clock
Q1
OST
SCS<1:0> bits Changed
Q2
TRANSITION TIMING TO RC_RUN MODE
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
= 1024 T
PC
Q3
Q4
OSC
Q1
. These intervals are not shown to scale.
Q1
T
1
OST
(1)
PC
2
Q2
Clock Transition
3
OSTS bit Set
Q3
PC + 2
n-1
Q4
PIC18F45J10 FAMILY
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTRC
while the primary clock is started. When the primary
clock becomes ready, a clock switch to the primary
clock occurs (see Figure 4-3). When the clock switch is
complete, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
n
Q1
Q2
PC + 2
Q3
Q2
Q4
Q3 Q4
Q1
Q1
PC + 4
Q2
PC + 4
Q2
DS39682E-page 37
Q3
Q3