ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 139
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.14.3
6.14.4
9111H–AUTO–01/11
Timer/Counter Clock Sources
Counter Unit
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0)
bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources
and prescaler (see
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter
unit.
Figure 6-41. Counter Unit Block Diagram
Signal description (internal signals):
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H)
containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower
eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU
does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary regis-
ter (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is
read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the
8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1
Register when the counter is counting that will give unpredictable results. The special cases
are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected
(CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,
independent of whether clk
counter clear or count operations.
Figure 6-41
Count
Direction
Clear
clk
TOP
BOTTOM
T
TCNTnH (8-bit)
1
TEMP (8-bit)
TCNTn (16-bit Counter)
DATA BUS (8-bit)
shows a block diagram of the counter and its surroundings.
“Timer/Counter0 and Timer/Counter1 Prescalers” on page
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
Timer/Counter clock.
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
TCNTnL (8-bit)
T
1
is present or not. A CPU write overrides (has priority over) all
T
1
). The clk
Direction
Count
Clear
T
1
Atmel ATA6612/ATA6613
Control Logic
can be generated from an external or internal
TOP
BOTTOM
TOVn
(Int.Req.)
clk
Tn
Clock Select
Detector
(From Prescaler)
Edge
131).
Tn
139
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