ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 232
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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Figure 6-79. START, REPEATED START and STOP Conditions
SDA
SCL
START
STOP
START
REPEATED START
STOP
6.19.3.3
Address Packet Format
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits,
one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read
operation is to be performed, otherwise a write operation should be performed. When a Slave
recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth
SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the
Master’s request, the SDA line should be left high in the ACK clock cycle. The Master can then
transmit a STOP condition, or a REPEATED START condition to initiate a new transmission.
An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R
or SLA+W, respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by
the designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the
ACK cycle. A general call is used when a Master wishes to transmit the same message to sev-
eral slaves in the system. When the general call address followed by a Write bit is transmitted
on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the
ack cycle. The following data packets will then be received by all the slaves that acknowl-
edged the general call. Note that transmitting the general call address followed by a Read bit
is meaningless, as this would cause contention if several slaves started transmitting different
data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 6-80. Address Packet Format
Addr MSB
Addr LSB
R/W
ACK
SDA
SCL
1
2
7
8
9
START
Atmel ATA6612/ATA6613
232
9111H–AUTO–01/11
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