ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 144
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.14.7
144
Atmel ATA6612/ATA6613
Compare Match Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator
uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare
match. Secondly the COM1x1:0 bits control the OC1x pin output source.
simplified schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control
Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring
to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a sys-
tem reset occur, the OC1x Register is reset to “0”.
Figure 6-44. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or
output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direc-
tion Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is
visible on the pin. The port override function is generally independent of the Waveform Gener-
ation mode, but there are some exceptions. Refer to
page 155
The design of the Output Compare pin logic allows initialization of the OC1x state before the
output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of
operation (see
The COM1x1:0 bits have no effect on the Input Capture unit.
COMnx1
COMnx0
FOCnx
clk
I/O
and
Table 6-55 on page 156
“16-bit Timer/Counter Register Description” on page
Waveform
Generator
for details.
D
D
PORT
D
OCnx
DDR
Q
Q
Q
Table 6-53 on page
1
0
155).
Figure 6-44
155,
9111H–AUTO–01/11
Table 6-54 on
OCnx
Pin
shows a
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