ATA6612P-PLQW Atmel, ATA6612P-PLQW Datasheet - Page 63
![MCU W/LIN TXRX REG WTCHDG 48-QFN](/photos/6/82/68297/48-qfn_sml.jpg)
ATA6612P-PLQW
Manufacturer Part Number
ATA6612P-PLQW
Description
MCU W/LIN TXRX REG WTCHDG 48-QFN
Manufacturer
Atmel
Series
AVR® ATA66 LIN-SBCr
Datasheet
1.ATA6612-EK.pdf
(364 pages)
Specifications of ATA6612P-PLQW
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
ATA6x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA6612P-PLQW
Manufacturer:
UPI
Quantity:
230
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6.7.1
6.7.2
9111H–AUTO–01/11
Sleep Mode Control Register – SMCR
Idle Mode
The Sleep Mode Control Register contains control bits for power management.
Table 6-18.
Note:
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire
Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating.
This sleep mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
• Bits 7..4 Res: Reserved Bits
• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
• Bit 0 – SE: Sleep Enable
Initial Value
Read/Write
These bits are unused bits in the Atmel
zero.
These bits select between the five available sleep modes as shown in
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the
programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just
before the execution of the SLEEP instruction and to clear it immediately after waking up.
Bit
SM2
0
0
0
0
1
1
1
1
1. Standby mode is only recommended for use with external crystals or resonators.
Sleep Mode Select
R
7
–
0
SM1
0
0
1
1
0
0
1
1
R
6
–
0
R
5
–
0
CPU
SM0
0
1
0
1
0
1
0
1
and clk
R
4
–
0
®
Atmel ATA6612/ATA6613
FLASH
ATA6612/ATA6613, and will always read as
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
Reserved
Reserved
Standby
Reserved
, while allowing the other clocks to run.
SM2
R/W
3
0
(1)
SM1
R/W
2
0
SM0
R/W
1
0
Table
R/W
SE
0
0
6-18.
SMCR
63
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