PIC16LF707-I/P Microchip Technology, PIC16LF707-I/P Datasheet - Page 175

• Manufacturer Part Number: PIC16LF707-I/P
• Description: MCU 8BIT 14KB FLASH 5.5V 40PDIP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF707-I/P

• Core Size: 8-Bit
• Program Memory Size: 14KB (8K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 36
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC16LF
• No. Of I/o's: 36
• Ram Memory Size: 363Byte
• Cpu Speed: 20MHz
• No. Of Timers: 6
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: I2C, SPI, AUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 14 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.2.10
When the CKP bit is cleared, the SCL output is held
low once it is sampled low. Therefore, the CKP bit will
not stretch the SCL line until an external I
device has already asserted the SCL line low. The
SCL output will remain low until the CKP bit is set and
all other devices on the I
This ensures that a write to the CKP bit will not violate
the minimum high time requirement for SCL
(Figure 19-14).
FIGURE 19-14:
 2010 Microchip Technology Inc.
SSPCON
SDA
CKP
SCL
WR
CLOCK SYNCHRONIZATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLOCK SYNCHRONIZATION TIMING
2
C bus have released SCL.
DX
2
Master device
asserts clock
C master
Preliminary
PIC16F707/PIC16LF707
19.2.11
While in Sleep mode, the I
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
Master device
deasserts clock
SLEEP OPERATION
2
C module can receive
DS41418A-page 175
DX-1