ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 168
![MCU AVR 16K FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32U4-AUR
Manufacturer Part Number
ATMEGA32U4-AUR
Description
MCU AVR 16K FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
Quantity
Price
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15.12.4
7766F–AVR–11/10
TCCR4D – Timer/Counter4 Control Register D
Table 15-18. Compare Output Mode, Phase and Frequency Correct PWM Mode
• Bit 1 - FOC4D: Force Output Compare Match 4D
The FOC4D bit is only active when the PWM4D bit specify a non-PWM mode.
Writing a logical one to this bit forces a change in the Waveform Output (OCW4D) and the Out-
put Compare pin (OC4D) according to the values already set in COM4D1 and COM4D0. If
COM4D1 and COM4D0 written in the same cycle as FOC4D, the new settings will be used. The
Force Output Compare bit can be used to change the output pin value regardless of the timer
value. The automatic action programmed in COM4D1 and COM4D0 takes place as if a compare
match had occurred, but no interrupt is generated. The FOC4D bit is always read as zero.
• Bit 0 - PWM4D: Pulse Width Modulator D Enable
When set (one) this bit enables PWM mode based on comparator OCR4D.
• Bit 7 - FPIE4: Fault Protection Interrupt Enable
Setting this bit (to one) enables the Fault Protection Interrupt.
• Bit 6– FPEN4: Fault Protection Mode Enable
Setting this bit (to one) activates the Fault Protection Mode.
• Bit 5 – FPNC4: Fault Protection Noise Canceler
Setting this bit activates the Fault Protection Noise Canceler. When the noise canceler is acti-
vated, the input from the Fault Protection Pin (INT0) is filtered. The filter function requires four
successive equal valued samples of the INT0 pin for changing its output. The Fault Protection is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 4 – FPES4: Fault Protection Edge Select
This bit selects which edge on the Fault Protection pin (INT0) is used to trigger a fault event.
When the FPES4 bit is written to zero, a falling (negative) edge is used as trigger, and when the
FPES4 bit is written to one, a rising (positive) edge will trigger the fault.
Bit
Read/Write
Initial value
COM4D1..0
00
01
10
11
OCW4D Behavior
Normal port operation.
Cleared on Compare Match when up-counting.
Set on Compare Match when down-counting.
Cleared on Compare Match when up-counting.
Set on Compare Match when down-counting.
Set on Compare Match when up-counting.
Cleared on Compare Match when down-counting.
FPIE4
R/W
7
0
FPEN4
R/W
6
0
FPNC4
R/W
5
0
FPES4
R/W
4
0
FPAC4
R/W
3
0
FPF4
R/W
2
0
ATmega16/32U4
Disconnected
Connected
Connected
Connected
OC4D Pin
WGM41
R/W
1
0
WGM40
R/W
0
0
Disconnected
Disconnected
Disconnected
Connected
OC4D Pin
TCCR4D
168
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