ATMEGA32U4-AUR Atmel, ATMEGA32U4-AUR Datasheet - Page 74
![MCU AVR 16K FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA32U4-AUR
Manufacturer Part Number
ATMEGA32U4-AUR
Description
MCU AVR 16K FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16U4-MU.pdf
(433 pages)
Specifications of ATMEGA32U4-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
26
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7766F–AVR–11/10
• SCK/PCINT1 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is
enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB1 bit.
PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.
• SS/PCINT0 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.
Table 10-4
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source..
Table 10-4.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 10-5 on page
PB7/PCINT7/OC0A/
OC1C/RTS
0
0
0
0
OC0/OC1C
ENABLE
OC0/OC1C
PCINT7 • PCIE0
1
PCINT7 INPUT
–
and
Overriding Signals for Alternate Functions in PB7.PB4
Table 10-5
relate the alternate functions of Port B to the overriding signals
70. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/PCINT6/OC1
B/OC.4B/ADC13
0
0
0
0
OC1B ENABLE
OC1B
PCINT6 • PCIE0
1
PCINT6 INPUT
–
PB5/PCINT5/OC1
A/OC.4B/ADC12
0
0
0
0
OC1A ENABLE
OC1A
PCINT5 • PCIE0
1
PCINT5 INPUT
–
ATmega16/32U4
PB4/PCINT4/A
DC11
0
0
0
0
0
0
PCINT4 • PCIE0
1
PCINT4 INPUT
–
74
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