ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 205

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19. TWI – Two Wire Interface
19.1
19.2
8077H–AVR–12/09
Features
Overview
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The Two Wire Interface (TWI) is bi-directional 2-wire bus communication, which is I
SMBus compatible.
A device connected to the bus must act as a master or slave.The master initiates a data transac-
tion by addressing a slave on the bus, and telling whether it wants to transmit or receive data.
One bus can have several masters, and an arbitration process handles priority if two or more
masters try to transmit at the same time.
The TWI module in XMEGA implements both master and slave functionality. The master and
slave functionality are separated from each other and can be enabled separately. They have
separate control and status register, and separate interrupt vectors. Arbitration lost, errors, colli-
sion and clock hold on the bus will be detected in hardware and indicated in separate status
flags available in both master and slave mode.
The master module contains a baud rate generator for flexible clock generation. Both 100 kHz
and 400 kHz bus frequency at low system clock speed is supported. Quick Command and Smart
Mode can be enabled to auto trigger operations and reduce software complexity.
For the slave, 7-bit and general address call recognition is implemented in hardware. 10-bit
addressing is also supported. A dedicated address mask register can act as a second address
match register or as a mask register for the slave address to match on a range of addresses.
The slave logic continues to operate in all sleep modes, including Power down. This enables the
slave to wake up from sleep on TWI address match. It is possible to disable the address match-
ing and let this be handled in software instead. This allows the slave to detect and respond to
several addresses. Smart Mode can be enabled to auto trigger operations and reduce software
complexity.
The TWI module includes bus state logic that collects information to detect START and STOP
conditions, bus collision and bus errors. This is used to determine the bus state (idle, owner,
busy or unknown) in master mode. The bus state logic continues to operate in all sleep modes
including Power down.
Fully Independent Master and Slave Operation
Multi-Master, Single Master, or Slave Only Operation
Phillips I
SMBus compatible
100 kHz and 400 kHz support at low system clock frequencies
Slew-Rate Limited Output Drivers
Input Filter provides noise suppression
7-bit, and General Call Address Recognition in Hardware
Address mask register for address masking or dual address match
10-bit addressing supported
Optional Software Address Recognition Provides Unlimited Number of Slave Addresses
Slave can operate in all sleep modes, including Power Down
Support for Arbitration between START/Repeated START and Data Bit (SMBus)
Slave Arbitration allows support for Address Resolve Protocol (ARP) (SMBus)
2
C compatible
XMEGA A
2
C and
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