PIC18F6490-E/PT Microchip Technology, PIC18F6490-E/PT Datasheet - Page 47

• Manufacturer Part Number: PIC18F6490-E/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6490-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• For Use With: DM163028 - BOARD DEMO PICDEM LCD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3.3
The
PIC18F6390/6490/8390/8490 devices is identical to
the legacy Sleep mode offered in all other PIC devices.
It is entered by clearing the IDLEN bit (the default state
on device Reset) and executing the SLEEP instruction.
This
Figure 3-5). All clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the primary clock source becomes ready (see
Figure 3-6), or it will be clocked from the internal oscil-
lator block if either the Two-Speed Start-up or the
Fail-Safe Clock Monitor are enabled (see Section 23.0
“Special Features of the CPU”). In either case, the
OSTS bit is set when the primary clock provides the
device clocks. The IDLEN and SCS bits are not
affected by the wake-up.
FIGURE 3-5:
FIGURE 3-6:
© 2007 Microchip Technology Inc.
Peripheral
Program
Counter
OSC1
Clock
Clock
Sleep
CPU
Note 1: T
shuts
CPU Clock
Peripheral
power-managed
PLL Clock
Program
Sleep Mode
Counter
Output
OSC1
Clock
Q1
down
OST
Q2
PC
= 1024 T
Q3
Wake Event
the
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
OSC
Q1
Sleep
selected
; T
Q1
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
mode
oscillator
PC
T
PLL
OSTS bit Set
PIC18F6390/6490/8390/8490
in
(1)
(see
the
Q2 Q3 Q4 Q1 Q2
PC + 2
3.4
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction
is executed, the peripherals will be clocked from the
clock source selected using the SCS1:SCS0 bits;
however, the CPU will not be clocked. The clock source
status bits are not affected. Setting IDLEN and execut-
ing SLEEP provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
(parameter 38, Table 26-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS1:SCS0 bits.
PC + 2
Q3 Q4 Q1 Q2
Idle Modes
PC + 4
Q3 Q4
Q1 Q2 Q3 Q4
PC + 6
DS39629C-page 45
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