PIC18F6490-E/PT Microchip Technology, PIC18F6490-E/PT Datasheet - Page 48

• Manufacturer Part Number: PIC18F6490-E/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6490-E/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, LCD, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• For Use With: DM163028 - BOARD DEMO PICDEM LCD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

PIC18F6390/6490/8390/8490
3.4.1
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing-sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
FIGURE 3-7:
FIGURE 3-8:
DS39629C-page 46
CPU Clock
Peripheral
CPU Clock
Program
Peripheral
Counter
Program
Counter
OSC1
Clock
OSC1
Clock
PRI_IDLE MODE
Q1
Q1
TRANSITION TIMING FOR ENTRY TO PRI_IDLE MODE
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Wake Event
Q2
PC
Q3
T
CSD
Q4
Q1
PC
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
PC + 2
Q2
© 2007 Microchip Technology Inc.
Q3
Q4
CSD
is