ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 177
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (6Mb)
Table 19-1.
19.4
Table 19-2.
7799D–AVR–11/10
Operating Mode
Synchronous Master mode
UCPOLn
SPI Data Modes and Timing
0
0
1
1
Equations for Calculating Baud Rate Register Setting
UCPOLn and UCPHAn Functionality-
UCPHAn
Note:
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in
all ongoing communication for both the Receiver and Transmitter.
Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.
0
1
0
1
BAUD
f
UBRRn
OSC
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
XCK
XCK
Data sample (RXD)
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Equation for Calculating Baud Rate
Figure
BAUD
19-1. Data bits are shifted out and latched in on opposite edges of the XCKn
SPI Mode
=
Table
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
0
1
2
3
UCPOL=0
-------------------------------------- -
2 UBRRn
(
19-2. Note that changing the setting of any of these bits will corrupt
f
OSC
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
+
1
)
(1)
ATmega8U2/16U2/32U2
Data setup (TXD)
Data sample (RXD)
Data setup (TXD)
Data sample (RXD)
XCK
XCK
Equation for Calculating UBRRn Value
UBRRn
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Trailing Edge
UCPOL=1
=
------------------- - 1
2BAUD
f
OSC
–
177
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