ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 202
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 202 of 309
- Download datasheet (6Mb)
21.11.2
21.12 CONTROL endpoint management
21.12.1
7799D–AVR–11/10
STALL handshake and Retry mechanism
Control Write
The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ request bit is set and if there is no retry required.
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-
rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall
thus never use them on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
CONTROL endpoints should not be managed by interrupts, but only by polling the status bits.
The next figure shows a control write transaction. During the status stage, the controller will not
necessary send a NAK at the first IN token:
• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware
• If the firmware knows the exact number of descriptor bytes that must be read, it can then
• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the
USB line
RXSTPI
RXOUTI
TXINI
acknowledge the packet and to clear the endpoint bank.
acknowledge the packet and to clear the endpoint bank.
to send the packet and to clear the endpoint bank.
anticipate on the status stage and send a ZLP for the next IN token,
host, and the transaction is now in the status stage.
SETUP
SETUP
HW
SW
OUT
HW
SW
DATA
ATmega8U2/16U2/32U2
OUT
HW
SW
NAK
IN
STATUS
SW
IN
202
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