ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 225
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 225 of 309
- Download datasheet (6Mb)
22.2.2
22.2.3
7799D–AVR–11/10
ACMUX – Analog Comparator Input Multiplexer
DIDR1 – Digital Input Disable Register 1
Table 22-1.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
• Bit 2, 0 – CMUX2:0: Analog Comparator Selection Bits
The value of these bits selects which combination of analog inputs are connected to the analog
comparator.
The different settings are shown in
Table 22-2.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AINx pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
Bit
(0x7D)
Read/Write
Initial Value
Bit
Read/Write
Initial Value
CMUX2
ACIS1
0
0
1
1
0
0
0
0
1
1
1
1
ACIS1/ACIS0 Settings
CMUX2:0 Settings
R
CMUX1
R
7
–
0
7
–
0
ACIS0
0
1
0
1
0
0
1
1
0
0
1
1
AIN6D
R/W
R
6
–
0
6
0
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
CMUX0
AIN5D
0
1
0
1
0
1
0
1
R/W
Table
R
5
–
0
5
0
22-2.
AIN4D
Comparator Input
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
Reserved
Reserved
R/W
R
4
–
0
4
0
ATmega8U2/16U2/32U2
AIN3D
R/W
R
3
–
0
3
0
CMUX2
AIN2D
R/W
R/W
2
0
2
0
CMUX1
AIN1D
R/W
R/W
1
0
1
0
CMUX0
AIN0D
R/W
R/W
0
0
0
0
ACMUX
DIDR1
225
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