ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 192
ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 192 of 309
- Download datasheet (6Mb)
20.5.3
20.6
7799D–AVR–11/10
Memory management
Freeze clock
EPEN=1
ALLOC=1
The firmware has the ability to freeze the clock of USB controller by setting the FRZCLK bit, and
thereby reduce the power consumption. When FRZCLK is set, it is still possible to access to the
following registers:
When FRZCLK is set, only the asynchronous interrupt may be triggered:
The controller does only support the following memory allocation management.
The reservation of an Endpoint can only be made in the increasing order (Endpoint 0 to the last
Endpoint). The firmware shall thus configure them in the same order.
The reservation of an Endpoint k
cates the memory and insert it between the Endpoints k
“slides” up and its data is lost. Note that the k
Clearing an Endpoint enable (EPEN) does not clear either its ALLOC bit, or its configuration
(EPSIZE/PSIZE, EPBK/PBK). To free its memory, the firmware should clear ALLOC. Then, the
k
does not slide.
The following figure illustrates the allocation and reorganization of the USB memory in a typical
example:
Table 20-1.
i+1
Free memory
• USBCON
• DPRAM direct access registers (DPADD7:0, UEDATX)
• UDCON
• UDINT
• UDIEN
• WAKEUPI
Endpoints
activation
Endpoint memory automatically slides down. Note that the k
4
3
2
1
0
Allocation and reorganization USB memory flow
Endpoint Disable
Free memory
(ALLOC=1)
EPEN=0
4
3
1
0
i
is done when its ALLOC bit is set. Then, the hardware allo-
i+2
Free its memory
Free memory
Lost memory
(ALLOC=0)
and upper Endpoint memory does not slide.
ATmega8U2/16U2/32U2
4
3
1
0
i-1
and k
i+2
i+1
and upper Endpoint memory
. The k
2 (bigger size)
Free memory
Activatation
Endpoint
3
1
0
4
i+1
Endpoint memory
Conflict
192
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