ATMEGA8HVA-4TU Atmel, ATMEGA8HVA-4TU Datasheet - Page 131
ATMEGA8HVA-4TU
Manufacturer Part Number
ATMEGA8HVA-4TU
Description
MCU AVR 8K FLASH 4MHZ 28-TSOP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16HVA-4CKU.pdf
(196 pages)
Specifications of ATMEGA8HVA-4TU
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
7
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 9 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
28-TSOP
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.9.6
23.9.7
23.9.8
8024A–AVR–04/08
BPSCD – Battery Protection Short-circuit Detection Level Register
BPDOCD – Battery Protection Discharge-Over-current Detection Level Register
BPCOCD – Battery Protection Charge-Over-current Detection Level Register
• Bits 7:0 – SCDL7:0: Short-circuit Detection Level
These bits sets the R
as defined in
Note:
• Bits 7:0 – DOCDL7:0: Discharge Over-current Detection Level
These bits sets the R
Table 23-5 on page
Note:
• Bits 7:0 –COCDL7:0: Charge Over-current Detection Level
These bits sets the R
Table 23-5 on page
Note:
Bit
(0xF5)
Read/Write
Initial Value
Bit
(0xF6)
Read/Write
Initial Value
Bit
(0xF7)
Read/Write
Initial Value
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPSCD register is written. Any
writing to the BPSCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPDOCD register is written. Any
writing to the BPDOCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of 3 ULP oscillator
cycles + 3 CPU clock cycles is required between each time the BPCOCD register is written. Any
writing to the BPCOCD register during this period will be ignored.
Table 23-5 on page
R/W
R/W
R/W
7
1
7
1
7
1
132.
132.
SENSE
SENSE
SENSE
R/W
R/W
R/W
6
1
6
1
6
1
voltage level for detection of Short-circuit in the discharge direction,
voltage level for detection of Discharge Over-current, as defined in
voltage level for detection of Charge Over-current, as defined in
132.
R/W
R/W
R/W
5
1
5
1
5
1
R/W
R/W
R/W
4
1
4
1
4
1
DOCDL[7:0]
COCDL[7:0]
SCDL[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
ATmega8HVA/16HVA
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
1
1
1
1
1
R/W
R/W
R/W
0
1
0
1
0
1
BPDOCD
BPCOCD
BPSCD
131
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